Thin film transistor substrate and manufacturing method thereof
View Patent ↗A thin film transistor array panel according to an exemplary embodiment of the present invention comprises a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, and a data line formed on the semiconductor layer, wherein the data line comprises a lower data layer, an upper data layer, a data oxide layer, and a buffer layer, wherein the upper data layer and the buffer layer comprise a same material.
1. A method for manufacturing a thin film transistor array panel, comprising:
forming a gate line on a substrate;
forming a gate insulating layer on the gate line;
sequentially forming an amorphous silicon layer, a lower data metal layer, and an upper data metal layer on the gate insulating layer;
forming a first photosensitive film pattern on the upper data metal layer;
identifying a defect in the first photosensitive film pattern;
removing the first photosensitive film pattern upon identifying the defect in the first photosensitive film pattern;
forming a buffer metal layer on the upper data metal layer; and
forming a second photosensitive film pattern on the buffer metal layer.
2. The method of claim 1 , further comprising sequentially forming an amorphous silicon layer doped with impurities on the amorphous silicon layer.
3. The method of claim 1 , wherein the first and second photosensitive film patterns each comprise first and second portions having different thicknesses.
4. The method of claim 1 , wherein the first photosensitive film pattern is removed using an organic solvent.
5. The method of claim 1 , wherein a residue of the first photosensitive film pattern on the upper data metal layer is removed using one of a hydrogen fluoride (HF) or an organic solvent.
6. The method of claim 1 , further comprising forming a data oxide layer on the upper data metal layer prior to forming the buffer metal layer.
7. The method of claim 1 , further comprising etching the upper and lower data metal layers via a first wet etching process, using the second photosensitive film pattern as a mask.
8. The method of 7 , further comprising etching the amorphous silicon layer via a first dry etching process, using the second photosensitive film pattern as a mask.
9. The method of 8 , further comprising:
forming a third photosensitive film pattern by ashing the second photosensitive film pattern; and
etching the upper data metal layer and the buffer metal layer via a second wet etching process, using the third photosensitive film pattern as a mask.
10. The method of 9 , further comprising etching the lower data metal layer and the amorphous silicon layer via a second dry etching process, using the third photosensitive pattern as a mask.
11. The method of claim 10 , further comprising:
removing the third photosensitive pattern;
forming a passivation layer on the substrate;
forming a contact hole in the passivation layer exposing a drain electrode; and
forming a pixel electrode on the passivation layer and in the contact hole.
12. The method of claim 1 , wherein the buffer metal layer is formed directly on the upper data metal layer.
13. The method of claim 1 , wherein the upper data metal layer comprises a first material, and the lower upper data metal layer comprises a second material different from the first material.