Field effect transistor with self-aligned source and heavy body regions and method of manufacturing same
A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches include a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.
1. A method of forming a FET, comprising:
forming a plurality of trenches simultaneously in a semiconductor region of a first conductivity type, the plurality of trenches comprising a plurality of gated trenches and a plurality of non-gated trenches;
forming a body region of a second conductivity in the semiconductor region between adjacent trenches;
filling a bottom portion of each of the gated and non-gated trenches with dielectric material;
forming a gate electrode in each gated trench over the dielectric material; and
forming a conductive material of the second conductivity type in each non-gated trench over the dielectric material such that the conductive material contacts the body region along sidewalls of each non-gated trench.
2. The method of claim 1 further comprising:
forming a source region of the first conductivity type in each body region, wherein the conductive material in each non-gated trench contacts corresponding source regions along sidewalls of the non-gated trench; and
forming a source interconnect layer contacting each source region and each conductive material.
3. The method of claim 1 wherein the filling step comprises:
filling each gated trench and each non-gated trench with dielectric material such that a top surface of the dielectric material in the gated and non-gated trenches is substantially co-planar with a top surface of mesa region adjacent the gated and non-gated trenches;
recessing the dielectric material in each gated trench to thereby form a thick bottom dielectric along a bottom portion of the gated trench; and
recessing the dielectric material in each non-gated trench to a depth above a depth of the body region.
4. The method of claim 1 wherein the step of forming a body region comprises:
performing a blanket implant of dopants of the second conductivity type in an active region of the FET.
5. The method of claim 2 wherein the step of forming a source region comprises:
performing a blanket implant of dopants of the first conductivity type in an active region of the FET.
6. The method of claim 1 wherein the semiconductor region comprises a highly doped substrate and an overlying epitaxial layer, and the body region is formed in an upper portion of the epitaxial layer.
7. The method of claim 1 wherein the step of forming a conductive material in each non-gated trench comprises:
forming a polysilicon layer to substantially fill each non-gated trench.
8. The method of claim 1 wherein one non-gated trench is formed between every two adjacent gated trench.
9. The method of claim 1 wherein two or more non-gated trenches are formed between every two adjacent gated trenches.