Multichannel interpolator

1. A system, comprising:

clock generator circuitry operable to receive an input clock representing a multichannel interpolated output signal frequency multiplied by a number of channels, generating a select signal and a plurality of output clocks;

a first stage multiplexer operable to receive a multichannel input signal for sampling and a first stage shift register output, a first stage multiplexer output being based on the select signal;

a first stage shift register operable to receive the first stage multiplexer output, said first stage shift register operable with said input clock to provide the first stage shift register output, said first stage shift register having a length that correlates to the number of channels;

one or more next stage multiplexers operable to receive a previous stage shift register output and a respective next stage shift register output, the one or more next stage multiplexer outputs being based on a select signal;

one or more next stage shift registers operable to receive a respective next stage multiplexer output and the said input clock, and to provide the respective next stage shift register output, said one or more next stage shift registers being the length of the first stage shift register, and wherein the number of shift registers and multiplexers is based upon a number of interpolation points;

a data store operable to provide impulse response coefficient;

a plurality of multipliers operable to multiply associated shift register output with impulse response coefficient; and

an adder operable to sum multiplier outputs thereby generating the multichannel interpolated output signal.

2. The system of claim 1 , wherein the clock generator circuitry is further operable to provide the select signal, at a rate lower than the input clock, to the multiplexer circuitry based on a carry out of a modulus 2 N accumulator incremented by an input word of one or more bits.

3. The system in claim 2 , wherein the clock generator circuitry is further operable to provide the accumulator bits to address the impulse response coefficients in the data store.

4. The system of claim 1 , wherein the data store is operable to provide impulse response coefficients to the multiplier circuitry associable with shift register outputs.

5. The system of claim 1 , wherein the data store is operable to provide the impulse response coefficients one bit in size.

6. The system of claim 1 , wherein the data store is operable to provide the impulse response coefficients two or more bits in size.

7. The system of claim 1 , wherein the data store is implemented with programmable volatile memory.

8. The system of claim 1 , wherein the data store is implemented with non-volatile memory.

9. The system of claim 1 , wherein the input signal, multiplexer, shift register, multiplier and adder circuitry are operable with a width of one bit.

10. The system of claim 1 , wherein the input signal, multiplexer, shift register, multiplier and adder circuitry operable with a width of two or more bits.

11. The system of claim 1 , wherein the multichannel input signal to the first stage multiplexer is a QAM (quadrature amplitude modulation) based signal.

12. A method comprising:

generating a select signal and a plurality of output clocks based on an input clock representing a multichannel interpolated output signal frequency multiplied by a number of channels;

generating a first stage multiplexer output between a multichannel input signal and a first stage shift register output based on the select signal;

generating a first stage shift register output based on said input clock and the first stage multiplexer output;

generating a next stage multiplexer output from between a previous stage shift register output and a next stage shift register output based on said select signal;

generating a next stage shift register output by one or more next stage shift registers, having a length correlating with the number of channels, with said input clock and wherein the number of shift registers and multiplexers is based upon a number of interpolation points;

multiplying associated shift register outputs with a impulse response coefficient; and

adding the multiplier outputs thereby generating the multichannel interpolated output signal.

13. The method of claim 12 , further comprising:

generating the select signal, at a rate lower than the input clock, based on a carry out of a modulus 2 N accumulator; and

incrementing the accumulator by an input word of one or more bits.

14. The method of claim 12 , further comprising:

providing accumulator bits to address the impulse response coefficients in the data store.

15. The method of claim 12 , further comprising:

providing the impulse response coefficients to multiplier circuitry associable with shift register outputs.

16. The method of claim 12 , further comprising:

providing the impulse response coefficients to the multiplier circuitry associable with shift register outputs.

17. The method of claim 12 , further comprising:

providing the impulse response coefficients one bit in size.

18. The method of claim 12 , further comprising:

providing the impulse response coefficients two or more bits in size.

19. The method of claim 12 , further comprising:

storing impulse response coefficients with programmable volatile memory.

20. The method of claim 12 , further comprising:

storing impulse response coefficients with programmable non-volatile memory.

21. The method of claim 12 , further comprising:

receiving a QAM (quadrature amplitude modulation) based input signal.