High current emitter drive unit cell
View Patent ↗A unit cell for a Read-In Integrated Circuit employs a signal sampling circuit with a voltage input controlled by a first switch, a capacitor charged by the voltage input and a linear amplifier connected to the capacitor. An output through a second switch samples the capacitor as the input signal for a transistor cascade for emitter current supply incorporating a first transistor receiving the input signal and a second transistor serially connected to the first transistor with a parallel resistor. The second transistor is maintained in saturation for a first portion of the input signal range with the first transistor acting as a source follower for that range. Linear current flow through the resistor results allowing high resolution control in the low current range. The second transistor departs saturation in a second portion of the range for the input signal resulting in saturation mode square-law behavior dominating the first transistor which, in turn, causes a rapid increase in current through its channel in response to higher input signal level thereby allowing a lower resolution but higher current for emitter drive at higher temperatures.
1. A unit cell for high current emitter drive in a Read-In Integrated Circuit comprising:
a signal sampling circuit creating a variable input signal having a desired range;
a transistor cascade for emitter current supply having a first transistor receiving the input signal and a second transistor serially connected to the first transistor with a parallel resistor, said second transistor maintained in saturation for a first portion of the input signal range, the first transistor acting as a source follower for the first range of the input signal with linear current flow through said resistor, said second transistor departing saturation in a second portion of the range for the input signal resulting in saturation mode square-law behavior dominating the first transistor, causing a rapid increase in current through its channel.
2. The unit cell as defined in claim 1 wherein the signal sampling circuit comprises:
a voltage input controlled by a first switch;
a capacitor charged by the voltage input;
a linear amplifier connected to the capacitor and providing an output through a second switch as the input signal for the first transistor.
3. The unit cell as defined in claim 2 a further comprising a reset switch to discharge the signal sampling circuit.
4. The unit cell as defined in claim 1 wherein the first and second transistor are current source devices.
5. The unit cell as defined in claim 1 wherein the first and second transistor are current sink devices.
6. The unit cell as defined in claim 1 further comprising a switch placing the second transistor in triode mode to eliminate linear current flow in the first portion of the input signal range.
7. The unit cell as defined in claim 1 wherein the first transistor is an extended-drain MOS device.
8. A method for high current emitter drive in a read-in integrated circuit unit cell comprising:
providing a variable input voltage;
providing an emitter current supply having a first transistor receiving the input voltage and a second transistor serially connected to the first transistor with a parallel resistor;
maintaining the second transistor in saturation for a first portion of the input signal range, the first transistor acting as a source follower for the first range of the input signal with linear current flow through said resistor;
departing saturation in the second transistor in a second portion of the range for the input signal; and
causing saturation mode square-law behavior to dominate the first transistor for a rapid increase in current through its channel in the second portion of the range of the input signal.
9. The method as defined in claim 8 wherein providing a variable input voltage comprises:
providing a variable voltage to a first switch;
charging a capacitor by the voltage input upon actuation of the first switch;
connecting a linear amplifier to the capacitor and
providing an output through a second switch as the input voltage for the first transistor.
10. The method as defined in claim 9 further comprising activating a reset switch to discharge the signal sampling circuit.