Mask and manufacturing method of a semiconductor device and a thin film transistor array panel using the mask
View Patent ↗An exposure mask is provided, which includes: a light blocking opaque area blocking incident light; a translucent area; and a transparent area passing the most of incident light, wherein the translucent area generates the phase differences in the range of about −70° to about +70°.
1. An exposure mask comprising:
a light blocking opaque area;
a translucent area; and
a transparent area;
wherein the translucent area generates a phase difference in an incident light passing through the transparent area,
wherein the phase difference is in the range between about −70° to about +70°; and
wherein the transmittance of the translucent area is about 20 and about 40 percent of the transmittance in the transparent area.
2. The exposure mask of claim 1 , wherein the light blocking opaque area is a coated layer of opaque material.
3. The exposure mask of claim 2 , wherein the translucent layer includes MoSi.
4. The exposure mask of claim 3 , wherein the translucent layer comprises at least one member selected from the group consisting of MoSiN, MoSiO, MoSiC, MoSiCO, MoSiCN, MoSiON, and MoSiCON.
5. The exposure mask of claim 2 , wherein the translucent layer includes a plurality of slits that are made of an opaque material.
6. The exposure mask of claim 2 , wherein the light blocking opaque layer includes Cr.
7. The exposure mask of claim 2 , wherein the translucent layer comprises about 0-20% C, 0-60% O, 0-60% N, and 20-60% Si by atomic weight, with the remainder being metal.