Thin film transistor array panel and manufacturing method thereof
View Patent ↗A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a gate electrode disposed on an insulation substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; an etching stop layer disposed on the semiconductor; an insulating layer disposed on the gate insulating layer; and a source electrode and a drain electrode overlapping the semiconductor. The semiconductor and the gate insulating layer have a first portion on which the etching stop layer and the insulating layer are disposed, and a second portion on which etching stop layer and the insulating layer are not disposed. The source electrode and the drain electrode are disposed on the second portion of the semiconductor and the gate insulating layer.
1. A thin film transistor array panel comprising:
a gate electrode disposed on an insulation substrate;
a gate insulating layer disposed on the gate electrode;
a semiconductor disposed on the gate insulating layer;
an etching stop layer disposed on a first portion of the semiconductor;
an insulating layer disposed on a second portion of the gate insulating layer; and
a source electrode and a drain electrode, the source and drain electrodes being disposed overlapping with the semiconductor,
wherein at least one of the source electrode and the drain electrode is disposed on a region comprising a third portion of the semiconductor and a fourth portion of the gate insulating layer, wherein the third portion of the semiconductor and the fourth portion of the gate insulating layer are not covered by either the etching stop layer or the insulating layer.
2. The thin film transistor array panel of claim 1 , wherein
the etching stop layer and the insulating layer are in the same layer.
3. The thin film transistor array panel of claim 2 , wherein
the semiconductor is an oxide semiconductor.
4. The thin film transistor array panel of claim 3 , wherein
the oxide semiconductor includes at least one of GIZO, ZTO (ZnSnO), and IZO.
5. The thin film transistor array panel of claim 3 , further comprising:
a gate line connected to the gate electrode;
a data line connected to the source electrode;
a passivation layer formed on the semiconductor and having a contact hole exposing the drain electrode; and
a pixel electrode formed on the passivation layer and connected to the drain electrode through the contact hole.
6. The thin film transistor array panel of claim 1 , wherein
the semiconductor is an oxide semiconductor.
7. The thin film transistor array panel of claim 6 , wherein
the oxide semiconductor includes at least one of GIZO, ZTO (ZnSnO), and IZO.
8. The thin film transistor array panel of claim 6 , further comprising:
a gate line connected to the gate electrode;
a data line connected to the source electrode;
a passivation layer formed on the semiconductor and having a contact hole exposing the drain electrode; and
a pixel electrode formed on the passivation layer and connected to the drain electrode through the contact hole.
9. The thin film transistor array panel of claim 1 , further comprising:
a gate line connected to the gate electrode;
a data line connected to the source electrode;
a passivation layer formed on the semiconductor and having a contact hole exposing the drain electrode; and
a pixel electrode formed on the passivation layer and connected to the drain electrode through the contact hole.