Low-voltage to high-voltage level translation using capacitive coupling
View Patent ↗A voltage level translator circuit has a digital logic circuit having a digital logic signal, at least one high-voltage capacitor having a first and second connection, wherein one of the first and second connections is electrically coupled to the digital logic signal, and a cross-coupled inverter pair having, the output of at least one inverter of the pair electrically coupled to the other connection of the at least one high-voltage capacitor. A high-voltage driving circuit has two low-voltage input signals, two high-voltage output signals, a first signal being a high-side drive signal and a second signal being a low-side drive signal, two level translators, a first level translator corresponding to the high-side drive signal, and a second level translator corresponding to the low-side drive signal, the level translators including a digital logic circuit having a digital logic signal, at least one high-voltage capacitor having a first and second connection, wherein one of the first and second connections is electrically coupled to the digital logic signal, and a cross-coupled inverter pair having, the output of at least one inverter of the pair electrically coupled to the other connection of the at least one high-voltage capacitor.
1. A voltage level translator circuit, comprising:
a digital logic circuit having a digital logic signal;
first and second high-voltage capacitors, each having a first and second connection, wherein one of the first and second connections is electrically coupled to the digital logic signal;
a cross-coupled inverter pair having the output of at least one inverter of the pair electrically coupled to the other connection of at least one of the first and second high-voltage capacitors;
a sensing circuit configured to sense the state of the cross-coupled inverter pair and to produce an output signal having a voltage level higher than the digital logic signal;
wherein the second capacitor has the first connection electrically coupled to the digital logic signal and the second connection electrically coupled to an output of the other of the at least one inverter of the pair;
wherein the electrical coupling of the digital logic signal to the first connection of the second capacitor includes logic inversion.
2. The voltage level translator circuit of claim 1 , wherein the at least one inverter of the cross-coupled inverter pair is weak by having high impedance relative to an impedance of the digital logic signal.
3. The voltage level translator circuit of claim 1 , wherein the cross-coupled inverter pair receives a reduced supply voltage compared to a supply voltage for the digital logic circuit.
4. The voltage translator circuit of claim 1 , further comprising a pseudo-differential receiver circuit arranged to sense a latch state of the cross-coupled inverter pair.
5. A high-voltage driving circuit, comprising:
two low-voltage input signals;
two high-voltage output signals, a first signal being a high-side drive signal and a second signal being a low-side drive signal;
two level translators, a first level translator generating the high-side drive signal, and a second level translator generating the low-side drive signal, the level translators comprising:
a digital logic circuit having a digital logic signal;
at least one high-voltage capacitor having a first and second connection, wherein one of the first and second connections is electrically coupled to the digital logic signal; and
a cross-coupled inverter pair having the output of at least one inverter of the pair electrically coupled to the other connection of the at least one high-voltage capacitor.
6. The high-voltage driving circuit of claim 5 , the level translators further comprising a sensing circuit configured to sense the state of the cross-coupled inverter pair.
7. The high-voltage driving circuit of claim 6 , the level translators further comprising a buffer configured to buffer an output of the sensing circuit.
8. The high-voltage driving circuit of claim 5 , wherein the at least one inverter of the cross-coupled inverter pair is weak by having high impedance relative to an impedance of the digital logic signal.
9. The high-voltage driving circuit of claim 5 , wherein the at least one high-voltage capacitor comprises first and second capacitors.
10. The high-voltage driving circuit of claim 9 , wherein the second capacitor has a first connection electrically coupled to the digital logic signal and a second connection electrically coupled to an output of the other of the at least one inverter of the pair.
11. The high-voltage driving circuit of claim 10 , wherein the electrical coupling of the digital logic signal to the first connection of the second capacitor includes logic inversion.
12. The high-voltage driving circuit of claim 9 , further comprising a pseudo-differential receiver circuit arranged to sense a latch state of the cross-coupled inverter pair.
13. The high-voltage driving circuit of claim 5 , further comprising a cross-conduction prevention circuit configured to detect simultaneous enabling of both the high-side drive signal and the low-side drive signal.
14. The high-voltage driving circuit of claim 13 , wherein an output of the cross-conduction prevention circuit resets an output of one of either the high-side level translator or the low-side level translator to an off state.
15. The high-voltage driving circuit of claim 5 , further comprising a power-on reset circuit to reset outputs of one of either the high-side level translator or the low-side level translator to an off state as power is applied to the circuit.