Substrate bias feedback scheme to reduce chip leakage power
View Patent ↗A substrate bias circuit may measure a leakage current of a baseline device, compare the leakage current with a reference current, and based on the comparison, adjust a reverse body bias voltage applied to a body of the baseline device.
1. A method, comprising:
measuring a leakage current of a baseline device;
comparing the leakage current with a reference current;
based on the comparison, controlling a charge pump to adjust a reverse body bias voltage applied to a body of the baseline device, wherein adjusting the reverse body bias voltage comprises modulating an output of a power supply supplying power to at least a portion of the charge pump.
2. The method of claim 1 , further comprising applying the reverse body bias voltage to a chip substrate.
3. The method of claim 1 , further comprising applying the reverse body bias voltage to a well of the baseline device, wherein the baseline device comprises a transistor.
4. The method of claim 1 , further comprising generating an analog control bias voltage based on the comparison.
5. The method of claim 4 , wherein generating the analog control bias voltage comprises varying a compare node potential based on a difference between a current capacity of a current source and a current capacity of the baseline transistor.
6. The method of claim 5 , wherein generating the analog control bias voltage further comprises establishing the current capacity of the current source using a reference bias voltage, and varying the current capacity of the baseline transistor in response to the reverse body bias voltage.
7. The method of claim 4 , wherein generating the analog control bias voltage comprises:
generating a compare input voltage in response to a difference between the reference current and the leakage current through the baseline device;
comparing the compare input voltage to a reference voltage to generate a compare result; and
increasing or decreasing the reverse body bias voltage in response to the compare result.
8. The method of claim 1 , wherein modulating the power supply is based on the comparison between the leakage current and the reference current.
9. The method of claim 1 , further comprising limiting the reverse body bias voltage to a maximum voltage.
10. The method of claim 1 , further comprising:
varying a control clock signal in response to the difference between the reference current and the current through the baseline transistor; and
generating the reverse body bias voltage in response to the control clock signal.
11. An apparatus, comprising:
a baseline device;
an amplifier block coupled with the baseline device, wherein the amplifier block is configured to generate an analog control bias voltage based on a difference between a leakage current of the baseline device and a reference current,
a charge pump circuit coupled with the baseline device, wherein the charge pump circuit is configured to adjust a reverse body bias voltage applied to a body of the baseline device based on the analog control bias voltage; and
a power supply coupled with at least a portion of the charge pump circuit, wherein the amplifier block is configured to adjust the reverse body bias voltage by modulating an output of the power supply.
12. The apparatus of claim 11 , wherein the charge pump is coupled with a chip substrate, and wherein the charge pump is further configured to apply the reverse body bias voltage to the chip substrate.
13. The apparatus of claim 11 , wherein the baseline device comprises a transistor, and wherein the charge pump circuit is further configured to apply the bias voltage to a well of the transistor.
14. The apparatus of claim 11 , wherein the amplifier block comprises:
an amplifier having an input coupled with the baseline device; and
a compare node coupled with an output of the amplifier, wherein the amplifier is configured to generate the analog control bias voltage by varying a potential of the compare node based on the difference between a current capacity of a current source and a current capacity of the baseline transistor.
15. The apparatus of claim 11 , wherein the amplifier block further comprises a voltage to current converter configured to convert a reference voltage to the reference current.
16. The apparatus of claim 11 , further comprising a clamp system coupled with the charge pump circuit, wherein the clamp system is configured to limit the reverse body bias voltage to a maximum voltage.
17. The apparatus of claim 11 , wherein the baseline device has a gate and a source-drain path coupled between a current source and a first power supply node.
18. The apparatus of claim 17 , wherein the current source comprises a source transistor having a conductivity type different from a conductivity type of the baseline transistor, and wherein a gate of the source transistor is coupled to receive a reference bias voltage, and wherein a source-drain path of the source transistor is coupled to the baseline transistor.
19. The apparatus of claim 11 , wherein the charge pump circuit comprises:
at least one charge pump cell configured to generate the reverse body bias voltage in response to a control clock signal, and
an analog clock driver configured to vary the control clock signal in response to the difference between the reference current and the current through the baseline transistor.