Semiconductor storage apparatus, and method and system for boosting word lines
View Patent ↗A semiconductor storage apparatus includes: a word line coupled to a cell transistor; a first capacitor having a first end coupled to the word line; a boost driver coupled to a second end of the first capacitor; a voltage-drop circuit configured to generate a given voltage drop between a first voltage and a second voltage; and a boost-drive circuit configured to boost a voltage at the second end from the second voltage to the first voltage.
1. A semiconductor storage apparatus comprising:
a word line coupled to a cell transistor;
a first capacitor having a first end coupled to the word line;
a boost driver coupled to a second end of the first capacitor;
a voltage-drop circuit configured to generate a given voltage drop between a first voltage and a second voltage; and
a boost-drive circuit, coupled to a second end of the first capacitor, configured to boost a voltage at the second end from the second voltage to the first voltage,
wherein the boost-drive circuit is provided between a first voltage supply that supplies the first voltage and a second voltage supply that supplies the second voltage, and the voltage-drop circuit generates the given voltage drop at a node between the boost-drive circuit and the second voltage supply,
wherein the voltage-drop circuit is disposed between the first supply voltage and the second supply voltage and includes a diode-coupled transistor,
wherein the diode-coupled transistor generates a voltage drop, and
wherein the voltage-drop circuit includes a second capacitor coupled to the diode-coupled transistor.
2. A semiconductor storage apparatus comprising:
a word line coupled to a cell transistor;
a first capacitor having a first end coupled to the word line;
a voltage-drop circuit configured to generate a given voltage drop between a first voltage and a second voltage; and
a boost-drive circuit, coupled to a second end of the first capacitor, configured to boost a voltage at the second end from the second voltage to the first voltage,
wherein the voltage-drop circuit is disposed between a first voltage supply and a second voltage supply and includes a diode-coupled transistor, and wherein the diode-coupled transistor generates a voltage drop,
wherein the voltage-drop circuit includes a second capacitor coupled to the diode-coupled transistor.
3. The semiconductor storage apparatus according to claim 2 , further comprising:
a switch circuit configured to discharge an electric charge of the second capacitor.
4. The semiconductor storage apparatus according to claim 1 , wherein the voltage-drop circuit includes a resistor coupled to the diode-coupled transistor.
5. A semiconductor storage apparatus comprising:
a word line coupled to a cell transistor;
a first capacitor having a first end coupled to the word line;
a boost driver coupled to a second end of the first capacitor;
a voltage-drop circuit configured to generate a given voltage drop between a first voltage and a second voltage; and
a boost-drive circuit, coupled to a second end of the first capacitor, configured to boost a voltage at the second end from the second voltage to the first voltage,
wherein the boost-drive circuit is provided between a first voltage supply that supplies the first voltage and a second voltage supply that supplies the second voltage, and the voltage-drop circuit generates the given voltage drop at a node between the boost-drive circuit and the second voltage supply;
wherein the voltage-drop circuit is disposed between the first supply voltage and the second supply voltage and includes a diode-coupled transistor;
wherein the diode-coupled transistor generates a voltage drop;
wherein the voltage-drop circuit includes a second capacitor coupled to the diode-coupled transistor;
wherein the voltage-drop circuit includes a resistor coupled to the diode-coupled transistor, and
wherein the voltage-drop circuit includes a third capacitor coupled to the diode-coupled transistor.
6. The semiconductor storage apparatus according to claim 1 ,
wherein the boost-drive circuit includes a PMOS transistor and an NMOS transistor that are coupled between the first voltage and the second voltage, and
wherein a coupling point between the PMOS transistor and the NMOS transistor is coupled to the second end.
7. A boost method of a word line comprising:
setting a word line to a first voltage which is supplied from a first voltage supply, the word line coupled to a first end of a capacitor;
generating, at node between one end of a boost-drive circuit and a second voltage supply which supplies a second voltage, a given voltage drop between a first voltage and a second voltage by a voltage drop circuit, the voltage drop circuit being disposed between the first supply voltage and the second supply voltage and including a diode-coupled transistor which generates a voltage drop and a second capacitor coupled to the diode-coupled transistor;
setting a word line to a given voltage; and
raising, by the boost-drive circuit, a voltage at a second end of the capacitor having a first end coupled to the word line from the second voltage to the first voltage after the word line is set to the first given voltage.
8. A system comprising:
a memory; and
a controller configured to control the memory,
wherein the memory includes:
a word line coupled to a cell transistor;
a first capacitor having a first end coupled to the word line;
a boost driver coupled to a second end of the first capacitor;
a voltage-drop circuit configured to generate a given voltage drop between a first voltage and a second voltage; and
a boost-drive circuit, coupled to a second end of the first capacitor, configured to boost a voltage at the second end from the second voltage to the first voltage,
wherein the boost-drive circuit is provided between a first voltage supply that supplies the first voltage and a second voltage supply that supplies the second voltage, and the voltage-drop circuit generates the given voltage drop at a node between the boost-drive circuit and the second voltage supply,
wherein the voltage-drop circuit is disposed between a first voltage supply and a second voltage supply and includes a diode-coupled transistor, and wherein the diode-coupled transistor generates a voltage drop,
wherein the voltage-drop circuit includes a second capacitor coupled to the diode-coupled transistor.
9. A semiconductor storage apparatus comprising:
a word line coupled to a cell transistor;
a first capacitor having a first end coupled to the word line;
a voltage-drop circuit configured to generate a given voltage drop between a first voltage and a second voltage; and
a boost-drive circuit configured to boost a voltage at a second end of the first capacitor from the second voltage to the first voltage,
wherein the boost-drive circuit includes a first transistor and a second transistor that are coupled between the first voltage and the second voltage,
wherein a coupling point between the first transistor and one end of the second transistor is coupled to the second end, and
wherein the voltage-drop circuit couples to the other end of the second transistor,
wherein the voltage-drop circuit is disposed between a first voltage supply and a second voltage supply and includes a diode-coupled transistor, and wherein the diode-coupled transistor generates a voltage drop,
wherein the voltage-drop circuit includes a second capacitor coupled to the diode-coupled transistor.
10. The semiconductor storage apparatus according to claim 9 , wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.