Flash memory storage system and method
View Patent ↗A flash memory storage system includes a memory array containing a plurality of memory cells and a controller for controlling the flash memory array. The controller dedicates a first group of memory cells to operate with a first number of bits per cell and a second, separate group of memory cells to operate with a second number of bits per cell. A mechanism is provided to apply wear leveling techniques separately to the two groups of cells to evenly wear out the memory cells.
1. A flash memory storage system comprising:
a memory array containing a plurality of memory cells; and
a controller for controlling said memory array by dedicating a first group of memory cells from among said plurality of memory cells to store a first number of bits per cell and dedicating a second group of memory cells from among said plurality of memory cells to store a second number of bits per cell, wherein said second number is greater than said first number, and said first group of memory cells and said second group of memory cells are disjoint; and
said controller applying a first wear leveling technique only within said first group of memory cells separately from said memory cells of said second group of memory cells, so as to evenly distribute wear of said first group of memory cells within themselves independent of wear of said second group of memory cell; and
wherein a ratio between a number of said memory cells of said second group of memory cells and a number of said memory cells of said first group of memory cells is set to equal a ratio between an endurance of said first group of memory cells and an endurance of said second group of memory cells multiplied by a ratio between said first number of bits and said second number of bits.
2. The flash memory storage system of claim 1 , wherein said controller is further operative to store data in said first group of memory cells and subsequently to copy said data into said second group of memory cells.
3. The flash memory storage system of claim 1 , wherein said first number of bits is one and said second number of bits is two.
4. The flash memory storage system of claim 1 , wherein said first number of bits is one and said second number of bits is four.
5. The flash memory storage system of claim 1 , further comprising said controller applying a second wear leveling technique only within said second group of memory cells, so as to evenly distribute wear of said second group of memory cells within themselves.