Electrical connectivity for circuit applications
View Patent ↗According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.
1. An integrated circuit device comprising:
a semiconductor layer including multiple transistors;
multiple interconnect layers connecting the multiple transistors in parallel;
a first conductive layer electrically coupled to the multiple transistors via the multiple interconnect layers, the first conductive layer being a material having a first resistivity;
a second conductive layer electrically coupled to the first conductive layer, the second conductive layer being a material having a second resistivity, the second resistivity being less than the first resistivity; and
the first conductive layer disposed between the semiconductor layer and the second conductive layer, the first conductive layer providing electrical connectivity between the multiple transistors connected in parallel and the second conductive layer;
wherein a first portion of the first conductive layer is a first common circuit node of the multiple transistors connected in parallel with each other;
wherein a second portion of the first conductive layer is a second common circuit node of the multiple transistors connected in parallel with each other;
wherein the first portion of the first conductive layer and the second portion of the first conductive layer are electrically isolated from each other;
wherein a first portion of the second conductive layer is electrically coupled to the first portion of the first conductive layer;
wherein a second portion of the second conductive layer is electrically coupled to the second portion of the first conductive layer;
wherein the first portion of the second conductive layer and the second portion of the second conductive layer are electrically isolated from each other;
a dielectric layer disposed between the first conductive layer and the second conductive layer;
a first field of multiple spaced conductive elements disposed in the dielectric layer to electrically connect the first portion of the first conductive layer to the first portion of the second conductive layer;
a second field of multiple spaced conductive elements disposed in the dielectric layer to electrically connect the second portion of the first conductive layer to the second portion of the second conductive layer;
wherein the multiple interconnect layers electrically connect a respective source node of each of the multiple transistors in the semiconductor layer to the first portion of the first conductive layer;
wherein the multiple interconnect layers electrically connect a respective drain node of each of the multiple transistors in the semiconductor layer to the second portion of the first conductive layer;
wherein a combination of the second conductive layer, the first conductive layer, and the multiple transistors form a stack;
wherein the first portion of the second conductive layer resides over the first portion of the first conductive layer, a first portion of the multiple transistors residing in the stack beneath the first portion of the first conductive layer; and
wherein the second portion of the second conductive layer resides over the second portion of the first conductive layer, a second portion of the multiple transistors residing in the stack beneath the first portion of the first conductive layer.
2. The integrated circuit device as in claim 1 , wherein the first conductive layer is aluminum and the second conductive layer is copper.
3. The integrated circuit device as in claim 1 further comprising:
a leadframe package, the leadframe package including a first conductive strip and a second conductive strip disposed in parallel;
a first conductive contact providing electrical connectivity between the first portion of the second conductive layer and the first conductive strip; and
a second conductive contact providing electrical connectivity between the second portion of the second conductive layer and the second conductive strip.
4. The integrated circuit device as in claim 1 , wherein the first portion of the first conductive layer resides adjacent to the second portion of the first conductive layer; and
wherein the first portion of transistors resides adjacent to the second portion of the transistors in the semiconductor layer.