IP Library Granted Patent US 8,358,940
Granted Patent B2
US 8,358,940 · App. 12/830,917 · Granted Jan 22, 2013

Method and system for optoelectronic receivers for uncoded data

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Quick Facts
Patent No.
US 8,358,940
App. No.
12/830,917
Granted
Jan 22, 2013
Kind
B2
Abstract

A method and system for optoelectronic receivers for uncoded data are disclosed and may include amplifying received electrical signals in a signal amplifier comprising differential gain stages with signal detectors coupled to the outputs. First and second output voltages may be tracked and held utilizing the signal detectors. A difference between the tracked and held value may be amplified in a feedback path of the gain stage, which enables the dynamic configuration of a decision level. The received electrical signals may be generated from an optical signal by a PIN detector, an avalanche photodiode, or a phototransistor. The electrical signal may be received from a read channel. The feedback path may comprise digital circuitry, including an A/D converter, a state machine, and a D/A converter. The detectors may comprise envelope detectors utilized to detect maximum or minimum voltages. The signal amplifier may be integrated in a photonically-enabled CMOS chip.

Claims (34)

1. A method for processing signals, the method comprising:

in a signal amplifier comprising one or more differential gain stages, two or more feedback paths, and two or more signal detectors coupled to outputs of one or more of said one or more differential gain stages:

amplifying received electrical signals utilizing one of said one or more differential gain stages;

tracking a value of a first sampled output signal and holding a value of a second sampled output signal of said one of said one or more differential gain stages utilizing said two or more signal detectors;

amplifying a difference between said tracked value of said first sampled output signal and said held value of said second sampled output signal in a first feedback path of said signal amplifier, and

controlling a mode of said signal detectors utilizing a second of said two or more feedback paths, wherein said two or more feedback paths enable the dynamic configuration of a decision level for said signal amplifier.

2. The method according to claim 1 , comprising generating said received electrical signals from a received optical signal.

3. The method according to claim 2 , comprising receiving said optical signal utilizing one or more of: a PIN photodiode, an avalanche photodiode, and a phototransistor.

4. The method according to claim 1 , comprising receiving said electrical signal from a read channel.

5. The method according to claim 1 , wherein said feedback path comprises digital circuitry.

6. The method according to claim 5 , wherein said digital circuitry comprises an analog-to-digital converter, a state machine, and a digital-to-analog converter.

7. The method according to claim 1 , wherein said two or more signal detectors comprise envelope detectors.

8. The method according to claim 7 , comprising detecting maximum voltages of said amplified received electrical signals utilizing said envelope detectors.

9. The method according to claim 7 , comprising detecting minimum voltages of said amplified received electrical signals utilizing said envelope detectors.

10. The method according to claim 1 , wherein said signal amplifier is integrated in a photonically-enabled CMOS chip.

11. The method according to claim 1 , wherein said signal detectors measure output voltages.

12. The method according to claim 1 , wherein said signal detectors measure output currents.

13. A system for processing signals, the system comprising:

one or more circuits in a signal amplifier comprising one or more differential gain stages, two or more feedback paths, and two or more signal detectors coupled to outputs of one or more of said one or more differential gain stages, said one or more circuits being operable to:

amplify received electrical signals utilizing one of said one or more differential gain stages;

track a value of a first sampled output signal and holding a value of a second sampled output signal of said one of said one or more differential gain stages utilizing said two or more signal detectors;

amplify a difference between said tracked value of said first sampled output signal and said held value of said second sampled output signal in a first feedback path of said signal amplifier, and

control a mode of said signal detectors utilizing a second of said two or more feedback paths, wherein said two or more feedback paths enable the dynamic configuration of a decision level for said signal amplifier.

14. The system according to claim 13 , wherein said one or more circuits are operable to generate said received electrical signals from a received optical signal.

15. The system according to claim 14 , wherein said one or more circuits are operable to receive said optical signal utilizing one or more of: a PIN photodiode, an avalanche photodiode, and a phototransistor.

16. The system according to claim 13 , wherein said one or more circuits are operable to receive said electrical signal from a read channel.

17. The system according to claim 13 , wherein said feedback path comprises digital circuitry.

18. The system according to claim 17 , wherein said digital circuitry comprises an analog-to-digital converter, a state machine, and a digital-to-analog converter.

19. The system according to claim 13 , wherein said two or more signal detectors comprise envelope detectors.

20. The system according to claim 19 , wherein said one or more circuits are operable to detect maximum voltages of said amplified received electrical signals utilizing said envelope detectors.

21. The system according to claim 19 , wherein said one or more circuits are operable to detect minimum voltages of said amplified received electrical signals utilizing said envelope detectors.

22. The system according to claim 13 , wherein said signal amplifier is integrated in a photonically-enabled CMOS chip.

23. The system according to claim 13 , wherein said signal detectors measure output voltages.

24. The system according to claim 13 , wherein said signal detectors measure output voltages.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 058979 FRAME: 0027. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 24, 2022
From: LUXTERA LLC
To: CISCO TECHNOLOGY, INC.
Reel/Frame 059496/0803 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2022
From: CISCO SYSTEMS, INC.
To: CISCO TECHNOLOGY, INC.
Reel/Frame 058979/0027 →
RELEASE OF SECURITY INTEREST Recorded Dec 24, 2020
From: SILICON VALLEY BANK
To: LUXTERA, LLC
Reel/Frame 054855/0838 →
CHANGE OF NAME Recorded Feb 6, 2020
From: LUXTERA, INC.
To: LUXTERA LLC
Reel/Frame 052019/0811 →
SECURITY INTEREST Recorded Mar 29, 2017
From: LUXTERA, INC.
To: SILICON VALLEY BANK
Reel/Frame 042109/0140 →
SECURITY AGREEMENT Recorded Feb 27, 2014
From: LUXTERA, INC.
To: SILICON VALLEY BANK
Reel/Frame 032364/0867 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2012
From: KUCHARSKI, DANIEL
To: LUXTERA INC.
Reel/Frame 029494/0717 →