Bit error rate reduction buffer, method and apparatus
View Patent ↗A disclosed example bit error rate reduction buffer comprises a data recovery circuit including differential bit pair inputs and differential bit pair outputs, a CRC circuit including differential bit pair inputs, differential bit pair outputs and a fault-isolation indicator, and a serializer including differential bit pair inputs and differential bit pair outputs. The differential bit pair outputs of the data recovery circuit being coupled to the differential bit pair inputs of the CRC circuit, the differential bit pair outputs of the CRC circuit being coupled to the differential bit pair inputs of the serializer, the differential bit pair inputs of the data recovery circuit to be driven by a first HSS link, the different bit pair outputs of the serializer to drive a second HSS link; and the fault-isolation indicator of the CRC circuit to indicate a fault when a fault is detected by the CRC circuit.
1. A bit error rate reduction buffer comprising:
a data recovery circuit including differential bit pair inputs and differential bit pair outputs;
a cyclic redundancy check (CRC) circuit including differential bit pair inputs, differential bit pair outputs and a fault-isolation indicator; and
a serializer including differential bit pair inputs and differential bit pair outputs;
the differential bit pair outputs of the data recovery circuit being coupled to the differential bit pair inputs of the CRC circuit; and
the differential bit pair outputs of the CRC circuit being coupled to the differential bit pair inputs of the serializer;
the differential bit pair inputs of the data recovery circuit to be driven by a first high speed serial (HSS) link;
the different bit pair outputs of the serializer to drive a second HSS link; and
the fault-isolation indicator of the CRC circuit to indicate a fault when a fault is detected by the CRC circuit.
2. The bit error rate reduction buffer as defined in claim 1 , wherein the data recovery circuit further includes a phase-locked loop.
3. A bit error rate reduction method, comprising:
transmitting differential signals along a first high speed serial link to a bit error rate reduction buffer, the bit error rate reduction buffer including:
a data recovery circuit including differential bit pair inputs and differential bit pair outputs;
a cyclic redundancy check (CRC) circuit including differential bit pair inputs, differential bit pair outputs and a fault-isolation indicator; and
a serializer including differential bit pair inputs and differential bit pair outputs;
the differential bit pair outputs of the data recovery circuit being coupled to the differential bit pair inputs of the CRC circuit;
the differential bit pair outputs of the CRC circuit being coupled to the differential bit pair inputs of the serializer;
the differential bit pair inputs of the data recovery circuit are to be driven by the first high speed serial link;
the different bit pair outputs of the serializer to drive a second high speed serial link; and
the fault-isolation indicator of the CRC circuit to indicate a fault when a fault is detected by the CRC circuit; and
after the differential signals have been operated on by the bit error rate reduction buffer, resending the differential signals along the second high speed serial link.
4. The bit error rate reduction method as defined in claim 3 , wherein the data recovery circuit comprises a phase-locked loop.
5. The bit error rate reduction method as defined in claim 3 , wherein the bit error rate reduction buffer, the first high speed serial link and the second high speed serial link couple a memory controller to a memory block.