Data processing apparatus including reconfigurable logic circuit
View Patent ↗There is provided a data processing apparatus ( 1 ) including a logic circuit ( 10 ) that is reconfigurable in each cycle and a library ( 2 ) that stores hardware control information ( 20 ). The hardware control information ( 20 ) includes a plurality of pieces of cycle-based mapping information ( 21 ) for individually mapping a plurality of cycle-based circuits, which each realize a function in each cycle for executing an application, onto the logic circuit ( 10 ) and configuration selection information ( 22 ) for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application. The data processing apparatus ( 1 ) includes a control unit ( 11 ) that reconfigures at least part of the logic region ( 10 ) using at least one of the plurality of pieces of cycle-based mapping information ( 21 ) according to a request in each cycle based on the configuration selection information ( 22 ).
1. A data processing apparatus comprising:
a logic circuit that is reconfigurable in each cycle; and
a library in which hardware control information is stored, wherein the hardware control information includes:
a plurality of pieces of cycle-based mapping information for mapping a plurality of cycle-based circuits onto the logic circuit individually, each of the plurality of cycle-based circuits realizing a function in each cycle for executing an application; and
configuration selection information for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application, and
the data processing apparatus further comprises:
a control unit that reconfigures, according to a request in each cycle based on the configuration selection information, at least part of the logic circuit using at least one of the plurality of pieces of cycle-based mapping information.
2. The data processing apparatus according to claim 1 , wherein the plurality of pieces of cycle-based mapping information include a piece of composite cycle-based mapping information produced by merging pieces of cycle-based mapping information that are capable of being merged without obstructing functions in each cycle.
3. The data processing apparatus according to claim 1 , wherein each of the plurality of pieces of cycle-based mapping information includes information for mapping a control unit for each cycle onto the logic circuit, and the control unit for each cycle is reconfigured in the logic circuit.
4. A non-transitory, computer-readable medium storing instructions for controlling a data processing apparatus, the data processing apparatus including a logic circuit that is reconfigurable in each cycle, a library in which hardware control information is stored, and a control unit that reconfigures at least part of the logic circuit, wherein the instructions, when executed by one or more processors of a computer system, cause the one or more processors to: reconfigure the at least part of the logic circuit based on the hardware control information stored in the library, wherein the hardware control information includes:
a plurality of pieces of cycle-based mapping information for mapping a plurality of cycle-based circuits onto the logic circuit individually, each of the plurality of cycle-based circuits realizing a function in each cycle for executing an application; and
configuration selection information for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application, and
select at least one of the plurality of pieces of cycle-based mapping information according to a request in each cycle based on the configuration selection information and reconfigure the at least part of the logic circuit using the selected at least one of the plurality of pieces of cycle-based mapping information.
5. The non-transitory, computer-readable medium of claim 4 , wherein each of the plurality of pieces of cycle-based mapping information includes information for mapping a control unit for each cycle onto the logic circuit, and wherein the instructions cause the one or more processors to reconfigure the at least part of the logic circuit by at least reconfiguring the at least part of the logic circuit according to a request of the control unit for each cycle that has been reconfigured in the logic circuit.