Summing circuit for a filter

1. A filter comprising:

a first bank clocked by a first sampling clock that receives an analog signal as input data and produces a first output signal, the first bank includes a first plurality of track and hold circuits, a first plurality of multipliers and a first summing circuit; and

a second bank clocked by a second sampling clock 180-degrees out of phase with the first sampling clock and receiving the analog signal as input data and produces a second output signal, the second bank includes a second plurality of track and hold circuits, a second plurality of multipliers and a second summing circuit,

wherein at least the first summing circuit comprises

a first load resistor coupled to a voltage source,

a second load resistor coupled to the voltage source,

a first cascode transistor including an emitter and a collector, the collector being coupled to the first load resistor,

a second cascode transistor including an emitter and a collector, the collector being coupled to the second load resistor,

a plurality of current offset circuits each coupled to the emitter of the first cascode transistor and the emitter of the second cascode transistor, and

a plurality of transconductance amplifiers in parallel and each corresponding to one of the plurality of current offset circuits.

2. The filter of claim 1 , wherein at least one of the first plurality of track and hold circuits comprises.

a first differential output terminal,

a unity gain amplifier,

a first transistor including a base, a collector and an emitter, the emitter being coupled to the first differential output terminal,

a first differential pair that comprises a second transistor having a collector coupled to the emitter of the first transistor and a third transistor including a collector coupled to the base of the first transistor and an emitter coupled to the emitter of the second transistor, and

a first isolation circuit coupled to the unity gain amplifier, the collector of the third transistor of the first differential pair and the base of the first transistor, the first isolation circuit to isolate parasitic capacitance from attenuating an output signal at the first differential output terminal.

3. A summing circuit comprising:

a first cascode transistor including an emitter;

a second cascode transistor including an emitter;

a first current offset circuit coupled to the emitter of the first cascode transistor and the emitter of the second cascode transistor;

a first transconductance amplifier coupled to the first current offset circuit;

a first load resistor coupled to a collector of the first cascade transistor;

a second load resistor coupled to a collector of the second cascade transistor;

a second current offset circuit in parallel with the first current offset circuit and coupled to the emitter of the first cascode transistor and the emitter of the second cascode transistor; and

a second transconductance amplifier in parallel with the first transconductance amplifier and coupled to the second current offset circuit.

4. A summing circuit comprising:

a first cascode transistor including an emitter;

a second cascode transistor including an emitter;

a first current offset circuit coupled to the emitter of the first cascode transistor and the emitter of the second cascode transistor;

a first transconductance amplifier coupled to the first current offset circuit;

a second current offset circuit in parallel with the first current offset circuit and coupled to the emitter of the first cascode transistor and the emitter of the second cascode transistor; and

a second transconductance amplifier in parallel with the first transconductance amplifier and coupled to the second current offset circuit.

5. The summing circuit of claim 4 further comprising:

a third current offset circuit in parallel with the first current offset circuit and the second current offset circuit, the third current offset circuit being coupled to the emitter of the first cascode transistor and the emitter of the second cascode transistor; and

a third transconductance amplifier in parallel with the first transconductance amplifier and the second transconductance amplifier, the third transconductance amplifier being coupled to the second current offset circuit.

6. A summing circuit, implemented within a filter and coupled to a track-and-hold circuit operating as a delay prior to an output of the summing circuit being applied to an output signal of the filter, the summing circuit comprising:

a first transistor including an emitter;

a second transistor including an emitter;

a first current offset circuit coupled to the emitter of the first transistor and the emitter of the second transistor; and

a first transconductance amplifier coupled to the first current offset circuit.

7. The summing circuit of claim 6 , wherein the first transistor is a cascade transistor.

8. The summing circuit of claim 7 , wherein the second transistor is a cascade transistor.

9. The summing circuit of claim 6 further comprising:

a first load resistor coupled to a collector of the first transistor;

a second load resistor coupled to a collector of the second transistor;

a second current offset circuit in parallel with the first current offset circuit and coupled to the emitter of the first transistor and the emitter of the second transistor; and

a second transconductance amplifier in parallel with the first transconductance amplifier and coupled to the second current offset circuit.

10. The summing circuit of claim 6 further comprising:

a second current offset circuit in parallel with the first current offset circuit and coupled to the emitter of the first transistor and the emitter of the second transistor; and

a second transconductance amplifier in parallel with the first transconductance amplifier and coupled to the second current offset circuit.

11. The summing circuit of claim 10 further comprising:

a third current offset circuit in parallel with the first current offset circuit and the second current offset circuit, the third current offset circuit being coupled to the emitter of the first transistor and the emitter of the second transistor; and

a third transconductance amplifier in parallel with the first transconductance amplifier and the second transconductance amplifier, the third transconductance amplifier being coupled to the third current offset circuit.