Systems and methods for tri-column code based error reduction
View Patent ↗Various systems and methods for tri-column code based error reduction are disclosed herein. For example, a digital information system is disclosed that includes channel detector. Such a channel detector receives an encoded data set and provides an output representing the encoded data set. The exemplary system further includes a decoder that receives the first output and is operable to perform three slope parity checks on the received first output. In turn, the decoder provides another output representing the encoded data set.
1. A method for data encoding, the method comprising:
receiving an un-encoded data set in a processing circuit, wherein the un-encoded data set is represented as an array of columns and rows;
identifying a first group of data bits traversing the un-encoded data set at a first angle;
identifying a second group of data bits traversing the un-encoded data set at a second angle;
identifying a third group of data bits traversing the un-encoded data set at a third angle;
calculating in the processing circuit a first parity for the first group of data bits, and assembling the first parity into a first column of parity bits;
calculating a second parity for the second group of data bits, and assembling the second parity into a second column of parity bits; and
calculating a third parity for the third group of data bits, and assembling the third parity into a third column of parity bits.
2. The method of claim 1 , wherein the first group of data bits includes one data bit from each column of the un-encoded data set.
3. The method of claim 1 , wherein calculating the first parity is exclusive of the second parity and exclusive of the third parity, wherein calculating the second parity is exclusive of the first parity and exclusive of the third parity, and wherein calculating the third parity is exclusive of the first parity and the second parity.
4. The method of claim 1 , wherein calculating the third parity includes using the first parity and the second parity.
5. The method of claim 4 , wherein calculating the second parity includes using the first parity, but is exclusive of the third parity.
6. The method of claim 1 , wherein the method further comprises:
providing the processing circuit, wherein the processing circuit is operable to perform: the receiving the un-encoded data set, the identifying the first group of data bits traversing the un-encoded data set at a first angle, the identifying a second group of data bits traversing the un-encoded data set at the second angle, the identifying the third group of data bits traversing the un-encoded data set at the third angle, the calculating the first parity for the first group of data bits, and assembling the first parity into the first column of parity bits, the calculating a second parity for the second group of data bits, and assembling the second parity into the second column of parity bits, and the calculating the third parity for the third group of data bits, and assembling the third parity into the third column of parity bits.
7. The method of claim 1 , wherein the first angle is different from at least one of the second angle and the third angle.
8. The method of claim 1 , wherein the first angle is the same as at least one of the second angle and the third angle.
9. The method of claim 1 , wherein the first angle is different from the second angle and different from the third angle.
10. The method of claim 1 , wherein the slope of at least one of the first angle, the second angle and the third angle are selected from a group consisting of: a slope greater than zero, a slope less than zero, and a slope equal to zero.
11. The method of claim 1 , wherein the method further includes programming at least one of the first angle, the second angle, or the third angle.
12. The method of claim 1 , wherein the data set is represented as columns and rows, and wherein the slope parity checks operate on at least one element from each of the columns.
13. A method for error reduction in a digital information system, the method comprising:
providing an encoder circuit, wherein the encoder circuit is operable to:
receive an un-encoded data set represented as an assay of columns and rows;
identify a first group of data bits traversing the un-encoded data set at a first angle;
identify a second group of data bits traversing the un-encoded data set at a second angle;
identify a third group of data bits traversing the un-encoded data set at a third angle;
calculate a first parity for the first group of data bits, and assemble the first parity into a first column of parity bits;
calculate a second parity for the second group of data bits, and assemble the second parity into a second column of parity bits; and
calculate a third parity for the third group of data bits, and assemble the third parity into a third column of parity bits.
14. A data encoder circuit, the data encoder circuit including circuitry operable to:
receive an un-encoded data set represented as an assay of columns and rows;
identify a first group of data bits traversing the un-encoded data set at a first angle;
identify a second group of data bits traversing the un-encoded data set at a second angle;
identify a third group of data bits traversing the un-encoded data set at a third angle;
calculate a first parity for the first group of data bits, and assemble the first parity into a first column of parity bits;
calculate a second parity for the second group of data bits, and assemble the second parity into a second column of parity bits; and
calculate a third parity for the third group of data bits, and assemble the third parity into a third column of parity bits.
15. The data encoder circuit of claim 14 , wherein the first group of data bits includes one data bit from each column of the un-encoded data set.
16. The data encoder circuit of claim 14 , wherein calculating the first
parity is exclusive of the second parity and exclusive of the third parity, wherein calculating the second parity is exclusive of the first parity and exclusive of the third parity, and wherein calculating the third parity is exclusive of the first parity and the second parity.
17. The data encoder circuit of claim 14 , wherein calculating the third parity includes using the first parity and the second parity.
18. The data encoder circuit of claim 17 , wherein calculating the second parity includes using the first parity, but is exclusive of the third parity.
19. The data encoder circuit of claim 14 , wherein the first angle is different from at least one of the second angle and the third angle.