Thin film transistor array panel and methods for manufacturing the same
View Patent ↗Disclosed is a simplified method for manufacturing a liquid crystal display. A gate wire including a gate line, a gate pad, and a gate electrode are formed on a substrate. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially deposited, and a photoresist layer is coated thereon. The photoresist layer is exposed to light through a mask and developed to form a photoresist pattern. At this time, a first portion of the photoresist pattern which is located between the source electrode and the drain electrode is thinner than a second portion which is located on the data wire, and the photoresist layer is totally removed on other parts. The thin portion is made by controlling the amount of irradiating light or by a reflow process to form a thin portion, and the amount of light is controlled by using a mask that has a slit, a small pattern smaller than the resolution of the exposure device, or a partially transparent layer. Next, the exposed portions of conductor layer are removed by wet etch or dry etch, and thereby the underlying ohmic contact layer is exposed. Then the exposed ohmic contact layer and the underlying semiconductor layer are removed by dry etching along with the first portion of the photoresist layer. The residue of the photoresist layer is removed by ashing. Source/drain electrodes are separated by removing the portion of the conductor layer at the channel and the underlying ohmic contact layer pattern. Then, the second portion of the photoresist layer is removed, and red, green, and blue color filters, a pixel electrode, a redundant gate pad, and a redundant data pad are formed.
1. A thin film transistor array panel comprising:
a substrate;
a gate line disposed on the substrate;
a data line crossing the gate line, and insulated from the gate line;
a thin film transistor electrically connected to the gate line and the data line respectively;
a first photosensitive layer having first color, and disposed on the thin film transistor;
a second photosensitive layer having second color different from the first color, and adjacent to the first photosensitive layer, the second color filter at least partially overlapping the first color filter; and
a pixel electrode electrically connected to the thin film transistor.
2. The thin film transistor array panel of claim 1 , further comprising a semiconductor layer disposed between the substrate and the data line.
3. The thin film transistor array panel of claim 2 , further comprising an insulating layer disposed between the photosensitive layers and the pixel electrode, a surface of the insulating layer contacting the pixel electrode being planar.
4. The thin film transistor array panel of claim 2 , wherein one of the first and the second colors is red, and another one of the first and the second colors is green.
5. The thin film transistor array panel of claim 2 , further comprising a storage electrode disposed on the same layer as the gate line.
6. The thin film transistor array panel of claim 5 , further comprising a conductor pattern overlapping the storage electrode, the conductor pattern disposed on the same layer as the data line.
7. A thin film transistor array panel comprising:
a substrate;
a gate line disposed on the substrate;
a data line crossing the gate line, and insulated from the gate line;
a thin film transistor electrically connected to the gate line and the data line respectively;
a first photosensitive layer having first color, and disposed on the thin film transistor;
a second photosensitive layer having second color different from the first color, and adjacent to the first photosensitive layer, the second color filter at least partially overlapping the first color filter ; and
a pixel electrode electrically connected to the thin film transistor, wherein one of the first and the second colors is red, and another one of the first and the second colors is green.
8. The thin film transistor array panel of claim 7 , further comprising a semiconductor layer disposed between the substrate and the data line.
9. The thin film transistor array panel of claim 8 , further comprising a storage electrode disposed on the same layer as the gate line.
10. The thin film transistor array panel of claim 9 , further comprising a conductor pattern overlapping the storage electrode, the conductor pattern disposed on the same layer as the data line.