High resolution A/D conversion based on piecewise conversion at lower resolution
View Patent ↗Piecewise conversion of an analog input signal is performed utilizing a plurality of relatively lower bit resolution A/D conversions. The results of this piecewise conversion are interpreted to achieve a relatively higher bit resolution A/D conversion without sampling frequency penalty.
1. An analog-to-digital (A/D) conversion method, comprising:
providing an analog input signal that varies within a voltage range over time;
associating portions of said voltage range to respectively corresponding A/D conversion operations;
performing said A/D conversion operations on the respectively corresponding portions to produce respectively corresponding multi-bit digital signal components having a common bit width, wherein each said multi-bit digital signal component varies in accordance with variation of the analog input signal only when the analog input signal occupies the corresponding portion of the voltage range; and
interpreting said multi-bit digital signal components to produce a composite digital signal that corresponds to the analog input signal and has a further bit width greater than said common bit width.
2. The method of claim 1 , wherein said associating includes providing respectively different bias voltages for controlling the respective A/D conversion operations.
3. The method of claim 2 , wherein said bias voltages are contained within said voltage range and substantially equally spaced from one another.
4. The method of claim 3 , wherein one of said bias voltages is substantially equal to an upper limit of said voltage range.
5. The method of claim 2 , wherein one of said bias voltages is substantially equal to an upper limit of said voltage range.
6. The method of claim 1 , wherein said multi-bit digital signal components are equal in number to 2 (R2−R1) , and wherein R 1 is said common bit width and R 2 is said further bit width.
7. The method of claim 6 , wherein said associating includes providing respectively different bias voltages for controlling the respective A/D conversion operations.
8. The method of claim 7 , wherein said bias voltages are contained within said voltage range and substantially equally spaced from one another.
9. The method of claim 7 , wherein one of said bias voltages is substantially equal to an upper limit of said voltage range.
10. The method of claim 1 , wherein said interpreting includes applying said multi-bit digital signal components as input to a look-up table.
11. An analog-to-digital (A/D) conversion apparatus, comprising:
a plurality of A/D conversion circuits arranged to receive an analog input voltage signal that varies within a voltage range over time, said A/D conversion circuits configured to perform respectively corresponding A/D conversion operations on respectively corresponding portions of said voltage range to produce respectively corresponding multi-bit digital signal components having a common bit width, wherein each said multi-bit digital signal component varies in accordance with variation of the analog input signal only when the analog input signal occupies the corresponding portion of the voltage range; and
an interpreter coupled to said A/D conversion circuits and configured to interpret said multi-bit digital signal components to produce a composite digital signal that corresponds to the analog input signal and has a further bit width greater than said common bit width.
12. The apparatus of claim 11 , wherein said A/D conversion circuits each respectively include an A/D converter and a bias circuit coupled to said A/D converter, and wherein said bias circuits provide respectively different bias voltages to the associated A/D converters for controlling the respective A/D conversion operations.
13. The apparatus of claim 12 , wherein said bias voltages are contained within said voltage range and substantially equally spaced from one another.
14. The apparatus of claim 13 , wherein one of said bias voltages is substantially equal to an upper limit of said voltage range.
15. The apparatus of claim 12 , wherein one of said bias voltages is substantially equal to an upper limit of said voltage range.
16. The apparatus of claim 11 , wherein said multi-bit digital signal components are equal in number to 2 (R2−R1) , and wherein R 1 is said common bit width and R 2 is said further bit width.
17. The apparatus of claim 16 , wherein said A/D conversion circuits each respectively include an A/D converter and a bias circuit coupled to said A/D converter, and wherein said bias circuits provide respectively different bias voltages to the associated A/D converters for controlling the respective A/D conversion operations.
18. The apparatus of claim 17 , wherein said bias voltages are contained within said voltage range and substantially equally spaced from one another.
19. The apparatus of claim 17 , wherein one of said bias voltages is substantially equal to an upper limit of said voltage range.
20. The apparatus of claim 11 , wherein said interpreter includes a look-up table and is configured to apply said multi-bit digital signal components as input to said look-up table.