Current sensing
A switching amplifier comprising: an output driving circuit ( 400 ) including a pair of switching transistors (M 1 , M 2 ) connected in series between a pair of supply voltage lines (V P , gnd); a switch driver circuit ( 204 a ) configured to drive the switching transistors (M 1 , M 2 ) with first and second respective PWM signals dependent on an input signal ( 101 ); an output connection between the pair of transistors (M 1 , M 2 ) for driving an output load ( 403 ); and an output current sensing circuit for measuring a current through the output load, the output current sensing circuit comprising: a current sensing resistor ( 401 a ) connected between a first one (M 2 ) of the pair of transistors and an adjacent supply voltage line (gnd); and a voltage sense circuit ( 404 ) connected across the current sensing resistor, wherein the voltage sense circuit is configured to sample a voltage across the current sensing resistor ( 401 a ) at a midpoint of successive corresponding portions of one of the PWM signals.
1. A switching amplifier comprising:
an output driving circuit including a pair of switching transistors connected in series between a pair of supply voltage lines;
a switch driver circuit configured to drive the switching transistors with first and second respective PWM signals dependent on an input signal;
an output connection between the pair of transistors for driving an output load; and
an output current sensing circuit for measuring a current through the output load, the output current sensing circuit comprising:
a current sensing resistor connected between a first one of the pair of transistors and an adjacent supply voltage line; and
a voltage sense circuit connected across the current sensing resistor,
wherein the voltage sense circuit is configured to sample a voltage across the current sensing resistor at a midpoint of successive corresponding portions of one of the PWM signals.
2. A switching amplifier comprising:
an output driving circuit including a pair of switching transistors connected in series between a pair of supply voltage lines;
a switch driver circuit configured to drive the switching transistors with first and second respective PWM signals dependent on an input signal;
an output connection between the pair of transistors for driving an output load; and
an output current sensing circuit for measuring a current through the output load, the output current sensing circuit comprising:
a current sensing resistor connected between a first one of the pair of transistors and an adjacent supply voltage line ;
a voltage sense circuit connected across the current sensing resistor,
wherein the voltage sense circuit is configured to sample a voltage across the current sensing resistor at a midpoint of successive corresponding portions of one of the PWM signals, and
wherein the voltage sense circuit comprises a PWM counter module and a track and hold circuit, the PWM counter module being configured to count a number of clock cycles of a positive portion of the first PWM signal and to trigger the track and hold circuit to sample the voltage across the current sensing resistor at a midpoint of a subsequent negative portion of the second PWM signal based on a subtraction of a number of clock cycles over a PWM period and the number of clock cycles of a positive portion of the first PWM signal.
3. The amplifier of claim 2 wherein the PWM counter module comprises:
a first counter configured to reset at each rising edge of the first PWM signal and count the number of clock cycles of the positive portion of the first PWM signal;
a subtractor module configured to subtract the number of clock cycles counted by the first counter from the number of clock cycles over the PWM period; and
a second counter configured to reset on each falling edge of the first PWM signal and count for half of a calculated number of clock cycles in a subsequent negative portion of the second PWM signal,
the second counter configured to provide a clock signal to the track and hold circuit to sample the voltage across the sensing resistor when half the number of clock cycles in the subsequent negative portion of the second PWM signal are counted.
4. The amplifier of claim 3 wherein the PWM counter module further comprises a multiplier module configured to receive the number of clock cycles of the negative portion of the second PWM signal from the subtraction module and provide half the number of clock cycles in the negative portion of the second PWM signal to the second counter.
5. The amplifier of claim 3 wherein the second counter is configured to count the number of clock cycles in the subsequent negative portion of the second PWM signal at twice a rate of the first counter.
6. A switching amplifier comprising:
an output driving circuit including a pair of switching transistors connected in series between a pair of supply voltage lines;
a switch driver circuit configured to drive the switching transistors with first and second respective PWM signals dependent on an input signal;
an output connection between the pair of transistors for driving an output load; and
an output current sensing circuit for measuring a current through the output load, the output current sensing circuit comprising:
a current sensing resistor connected between a first one of the pair of transistors and an adjacent supply voltage line ;
a voltage sense circuit connected across the current sensing resistor,
wherein the voltage sense circuit is configured to sample a voltage across the current sensing resistor at a midpoint of successive corresponding portions of one of the PWM signals, and
wherein the output driving circuit comprises a first pair and a second pair of switching transistors, each pair of switching transistors connected in series between the pair of supply voltage lines.
7. The amplifier of claim 6 wherein the pair of supply voltage lines are a voltage supply line and a ground line, the current sensing resistor connected between a first one of the first pair of switching transistors and the ground line.
8. The amplifier of claim 6 wherein the first one of each pair of switching transistors is an N-MOS transistor.
9. The amplifier of claim 7 , further comprising a second current sensing resistor connected between a first one of the second pair of switching transistors and the ground line.
10. The amplifier of claim 9 wherein the voltage sense circuit is configured to sample a differential voltage across the first and second current sensing resistors.
11. A method of sensing output current from a switching amplifier having an output driving circuit including a pair of switching transistors connected in series between a pair of supply voltage lines, the pair of switching transistors being driven by a switch driver circuit with first and second respective PWM signals dependent on an input signal, the method comprising: triggering a track and hold circuit to sample a voltage across a current sensing resistor connected between a first one of the pair of transistors and an adjacent supply voltage line at a midpoint of the subsequent negative portion of the second PWM signal.
12. A method of sensing output current from a switching amplifier having an output driving circuit including a pair of switching transistors connected in series between a pair of supply voltage lines, the pair of switching transistors being driven by a switch driver circuit with first and second respective PWM signals dependent on an input signal, the method comprising:
triggering a track and hold circuit to sample a voltage across a current sensing resistor connected between a first one of the pair of transistors and an adjacent supply voltage line at a midpoint of the subsequent negative portion of the second PWM signal;
counting a number of clock cycles of a positive portion of the first PWM signal;
calculating a number of clock cycles in a subsequent negative portion of the second PWM signal by subtracting the number of clock cycles of the positive portion from a number of clock cycles in a period of the PWM signals; and
calculating a midpoint of the subsequent negative portion of the second PWM signal by halving the calculated number of clock cycles in the negative portion of the second PWM signal.