Booster circuit
View Patent ↗A boosting circuit comprises a first boosting cell row and a second boosting cell row. The boosting circuit further comprises an analog comparison circuit for comparing the potential of boosting cells on the same stage, and selecting and outputting the lower or higher of the potentials. The potential of an N well is controlled using the output potential of the analog comparison circuit. Thereby, the amplitude of an N well potential can be suppressed, and a single N well region can be shared.
1. A booster circuit comprising:
a first boosting cell row including N stages (N≧1) of boosting cells;
a second boosting cell row including M stages (M≧1) of boosting cells; and
at least one analog comparison circuit for outputting a well bias potential generated by an input potential of the boosting cell on the i-th stage (1≦i≦N) of the first boosting cell row and an input potential of the boosting cell on the i-th stage (1≦i≦M) of the second boosting cell row, wherein:
each boosting cell includes a first-conductivity type first well region on a substrate, a second-conductivity type second well region in the first well region, and at least one switching element in either or both of the first well region and the second well region,
the at least one switching element is configured to transfer charges from a first terminal to a second terminal, and
the well bias potential of the at least one analog comparison circuit is applied to the first well region of the switching element included in the at least one boosting cell of the first and second boosting cell rows.
2. The booster circuit of claim 1 , wherein:
the first boosting cell row includes at least one backflow preventing circuit;
the second boosting cell row includes at least one backflow preventing circuit; and
the well bias potential of the at least one analog comparison circuit is applied to a first well region of a switching element included in the at least one backflow preventing circuit of the first and second boosting cell rows.
3. The booster circuit of claim 1 , wherein the well bias potential is the higher potential out of the input potential of the boosting cell on the i-th stage (1≦i≦N) of the first boosting cell row and the input potential of the boosting cell on the i-th stage (1≦i≦M) of the second boosting cell row.
4. The booster circuit of claim 1 , wherein the well bias potential is the lower potential out of the input potential of the boosting cell on the i-th stage (1≦i≦N) of the first boosting cell row and the input potential of the boosting cell on the i-th stage (1≦i≦M) of the second boosting cell row.
5. The booster circuit of claim 1 , wherein the second well region and the first terminal are connected to each other so that the second well region and the first terminal have the same potential.
6. The booster circuit of claim 1 , wherein the second well region and the first well region are connected to each other so that the second well region and the first well region have the same potential.
7. The booster circuit of claim 1 , wherein:
the at least one analog comparison circuit has a first-conductivity type first well region on the substrate, a second-conductivity type second well region in the first well region, and at least one switching element in the first well region or the second well region, and
the at least one analog comparison circuit is provided for each boosting cell stage in the first boosting cell row and the second boosting cell row.
8. The booster circuit of claim 1 , wherein:
the at least one analog comparison circuit has a first-conductivity type first well region on the substrate, a second-conductivity type second well region in the first well region, and at least one switching element in the first well region or the second well region, and
the at least one analog comparison circuit is provided for arbitrary number of boosting cell stages in the first boosting cell row and the second boosting cell row.
9. The booster circuit of claim 1 , wherein a diode element is provided between the first terminal and the first well region of the boosting cell.
10. The booster circuit of claim 1 , wherein:
the at least one switching element of the boosting cell on the i-th stage of the first boosting cell row and a first element of the at least one analog comparison circuit share a common first well region, and
the at least one switching element of the boosting cell on the i-th stage of the second boosting cell row and a second element of the at least one analog comparison circuit share a common first well region.
11. The booster circuit of claim 1 , wherein an output potential of the analog comparison circuit is applied to the first well region of the at least one switching element included in a boosting cell of a boosting cell row different from the first and second boosting cell rows.
12. A booster circuit comprising:
a first boosting cell row including N stages (N≧2) of boosting cells; and
a second boosting cell row including M stages (M≧2) of the boosting cells, wherein:
each boosting cell includes a first-conductivity type first well region on a substrate, a second-conductivity type second well region in the first well region, and at least one switching element in either or both of the first well region and the second well region,
the at least one switching element switches ON/OFF a connection between a first terminal and a second terminal so as to transfer charges from the first terminal to the second terminal,
a potential of the first well region of the at least one switching element included in the boosting cells on a second stage or stages succeeding the second stage in the first and second boosting cell rows is controlled according to an input potential of the boosting cells of the first boosting cell row and an input potential of the boosting cells of the second boosting cell row, and
an input potential of each of the boosting cells of the first boosting cell row is different from an input potential of each of the boosting cells of the second boosting cell row.