Memory embedded logic semiconductor device having memory region and logic circuit region
View Patent ↗In a method of manufacturing a semiconductor device, first contact holes reaching diffusion regions of a cell transistor, bit line contact holes reaching diffusion regions of the cell transistor, and interconnect grooves communicating with the bit line contact holes are buried in a first insulating film. In addition, first contact plugs and bit line contacts are respectively formed by burying conductive materials in the first contact holes, the bit line contact holes and the interconnect grooves, and the first contact plugs are electrically connected to a capacitor formed in a third insulating film through an opening formed in a second insulating film.
1. A method of manufacturing a semiconductor device, comprising:
forming a cell transistor in a memory region of a semiconductor substrate, and forming a logic device in a logic region of said semiconductor substrate;
forming a first insulating film for coating both said cell transistor and said logic device over said semiconductor substrate;
forming a bit line interconnect groove by selectively processing said first insulating film by etching;
forming a first contact hole reaching a first diffusion region of said cell transistor by selectively processing said first insulating film by etching, and forming a bit line contact hole which reaches a second diffusion region of said cell transistor and communicates with said interconnect groove;
forming a first contact plug by burying a conductive material in said first contact hole, and forming a bit line contact plug and a bit line, respectively, by burying a conductive material in said bit line contact hole and said interconnect groove;
forming a second insulating film for coating said first contact plug and said bit line over said first insulating film;
forming a first opening reaching said first contact plug by selectively processing said second insulating film by etching;
forming a third insulating film over said second insulating film after forming said first opening;
forming a concave portion communicating with said first opening by processing said third insulating film by etching; and
forming a capacitor, which is electrically connected to said first contact plug through said first opening, in said concave portion.
2. The method of manufacturing the semiconductor device as set forth in claim 1 , further comprising:
forming a second contact hole reaching said logic device by selectively processing said first insulating film by etching; and
forming a second contact plug by burying a conductive material in said second contact hole,
wherein said step of forming the first contact hole and said step of forming the second contact hole are simultaneously executed using the same mask pattern.
3. The method of manufacturing the semiconductor device as set forth in claim 2 ,
wherein said second insulating film is formed by the same step over both said memory region and said logic region.
4. The method of manufacturing the semiconductor device as set forth in claim 3 , further comprising forming a second opening reaching said second contact plug by selectively processing said second insulating film by etching,
wherein said step of forming the first opening and said step of forming the second opening are simultaneously executed using the same mask pattern.
5. The method of manufacturing the semiconductor device as set forth in claim 4 , further comprising:
forming a third contact hole communicating with said second opening by selectively processing said third insulating film by etching; and
forming a third contact plug by burying a conductive material in said third contact hole and said second opening.
6. The method of manufacturing the semiconductor device as set forth in claim 1 , further comprising planarizing the surface of a stacked structure including said first insulating film, said first contact plug and said bit line contact plug, immediately before said step of forming the second insulating film.
7. The method of manufacturing the semiconductor device as set forth in claim 1 , said second insulating film is a nitride film.
8. The method of manufacturing the semiconductor device as set forth in claim 1 , wherein said step of forming the capacitor includes:
forming a first electrode layer electrically connected to said first contact plug in said first opening and said concave portion;
forming a dielectric film for coating said first electrode layer; and
forming a second electrode layer over said dielectric film.