Semiconductor device
View Patent ↗A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.
1. A semiconductor device comprising:
a source region formed in a substrate, the substrate having a surface;
a drain region formed in the substrate;
a gate electrode formed above the surface of the substrate, the gate electrode being positioned between the source region and the drain region along a first direction which is a direction along the surface, the gate electrode having a first edge in a second direction which is a direction along the surface, the second direction intersects orthogonally with the first direction, the first edge extending along the first direction;
an impurity layer formed in the substrate, the impurity layer surrounding the gate electrode, the source region and the drain region in the plan view, the impurity layer having a ring shape in the plan view;
a layer formed above the impurity layer, the layer including a second edge in the second direction, the second edge extending along the first direction, the layer having a ring shape in the plan view; and
a first wiring layer formed above at least a part of a first region of the substrate, the first region being located between the first edge and the second edge in the plan view.
2. The device according to claim 1 ,
wherein the second direction and a length direction of the gate electrode are the same.
3. The device according to claim 2 ,
wherein the layer above the impurity layer includes a third edge in the second direction, the third edge extending along the first direction, and
wherein a first distance from the first edge to the second edge is shorter than a second distance from the first edge to the third edge.
4. The device according to claim 3 ,
wherein the first wiring layer electrically contacts the gate electrode.
5. The device according to claim 4 , further comprising:
a first contact layer formed on the gate electrode and contacting the gate electrode;
a second wiring layer formed on the first contact layer and contacting the first contact layer; and
a second contact layer formed on the second wiring layer and contacting the second wiring layer;
wherein the first wiring layer contacts the second contact layer.
6. The device according to claim 5 ,
wherein the impurity layer is a guard ring.
7. The device according to claim 1 ,
wherein a first length of the gate electrode in the first direction is shorter than a second length of the first wiring layer in the first direction.
8. The device according to claim 1 ,
wherein a first length of the gate electrode in the first direction is longer than a second length of the first wiring layer in the first direction.
9. The device according to claim 1 ,
wherein the layer is electrically connected with the impurity layer.