Granted Patent B2

US 8,555,050 · App. 12/836,962 · Granted Oct 8, 2013

Abstract

Claims (37)

1. An apparatus configured to enable booting from a NAND flash memory, the apparatus comprising:

a NAND flash controller configured to be connected to the NAND flash memory, wherein the NAND flash memory is configured to include at least a starter section including a predefined number of blocks to store copies of a boot code; and

a fetch emulator configured to identify a valid block, from among the predefined number of blocks, based on values of spare bytes on pages of the predefined number of blocks.

2. The apparatus of claim 1 , wherein the fetch emulator is configured to be connected to the NAND flash controller and to a central processing unit (CPU), wherein the CPU is configured to boot from the boot code contained in the valid block.

3. The apparatus of claim 1 , wherein the CPU is configured to be connected to an internal memory through a memory controller, and the NAND flash controller is configured to load a system initialization code, an, operating system image, and user data to the internal memory from the NAND flash memory.

4. The apparatus of claim 3 , wherein the NAND flash memory is further configured to include a system initialization code section, an operating system image section, and a user data section to respectively store the system initialization code, the operating system image, and the user data.

5. The apparatus of claim 1 , wherein the fetch emulator is further configured to identify a complete starter block which includes at least one other valid block from among the predefined number of blocks.

6. The apparatus of claim 1 , wherein the fetch emulator is further configured to:

map the identified valid block in the starter section;

read each page from the mapped valid block;

check whether the read page includes error bits; and

correct the error bits in the read page when it is determined that the read page includes error bits.

7. The apparatus of claim 6 , wherein the fetch emulator is configured to correct the error bits using an error correction codes (ECC) mechanism.

8. The apparatus of claim 6 , wherein the fetch emulator is further configured to sequentially access a next identified valid block in the starter section to read a page corresponding to a previously read page when it is determined that the error bits in the previously read page cannot be corrected using the ECC mechanism.

9. The apparatus of claim 8 , wherein the fetch emulator is configured to sequentially access additional identified valid blocks until a valid page including no error bits is read and the complete starter block includes only valid pages.

10. The apparatus of claim 8 , wherein all the predefined number of blocks substantially include the same content.

11. The apparatus of claim 6 , wherein the fetch emulator is further configured to save mapping information of identified valid blocks in a register.

12. The apparatus of claim 1 , wherein the predefined number of blocks is greater than two.

13. A method for ensuring booting from a NAND flash memory, the method comprising:

receiving a fetch instruction from a central processing unit (CPU) to retrieve a boot code;

identifying a valid block, from among a predefined number of blocks, based on values of spare bytes on pages of the predefined number of blocks, the predefined number of blocks being configured to store copies of the boot code, and to be included in a starter section that is part of the NAND flash memory; and

instructing the CPU to boot from the boot code that resides in the valid block.

14. The method of claim 13 , further comprising:

reading each page from the valid block in the starter section;

checking whether the read block includes error bits; and

correcting the error bits in the read page when it is determined that the read page includes error bits.

15. The method of claim 14 , wherein the correcting the error bits comprises correcting the error bits using an error correction codes (ECC) mechanism.

16. The method of claim 15 , further comprising:

accessing a next identified valid block in the starter section to read a page corresponding to a previously read page when it is determined that the error bits in the previously read page cannot be corrected using the ECC mechanism.

17. The method of claim 16 , wherein the accessing comprises sequentially accessing additional identified valid blocks until a valid page including no error bits is read and the complete starter block includes only valid pages.

18. The method of claim 16 , wherein all the predefined number of blocks substantially include the same content.

19. The method of claim 14 , further comprising:

mapping the identified valid block; and

saving information about the mapped valid block in a register.

20. The method of claim 13 , wherein the predefined number of blocks is greater than two.

21. The apparatus of claim 1 , wherein the fetch emulator, is configured to identify the valid block based on values of two spare bytes on a first two pages of the predetermined number of blocks.

22. The apparatus of claim 21 , wherein the fetch emulator is configured to identify the valid block when any of the values of the two spare bytes on the first two pages is not a zero.

Assignments (6)