Semiconductor memory device for storing multivalued data
View Patent ↗Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining the first memory cells in the bit line direction.
1. A method of operating the non-volatile semiconductor memory, the non-volatile semiconductor memory including a memory cell, the memory cell capable of storing n bits of data (n is a natural number equal to or larger than two), the method comprising:
receiving a first bit of data from the outside of an non-volatile semiconductor memory;
making a threshold voltage of the memory cell higher than a first level if the first bit of data is a first value;
receiving a second bit of data from the outside of the non-volatile semiconductor memory;
making the threshold voltage of the memory cell, that has been made higher than the first level, higher than a second level, if the second bit of data is a second value, the second level being higher than the first level; and
making the threshold voltage of the memory cell, that has been made higher than the first level, higher than a third level, if the second bit of data is a third value, the third level being higher than the second level, the third value differing from the second value,
wherein the step of making the threshold voltage of the memory cell higher than the first level comprises:
applying a first program voltage to the memory cell to alter the threshold voltage of the memory cell;
determining whether the threshold voltage of the memory cell is lower than the first level; and
applying a second program voltage to the memory cell to alter the threshold voltage of the memory cell if it has been determined that the threshold voltage of the memory cell is lower than the first level, the second program voltage being higher than the first program voltage by a first amount, and
wherein the step of making the threshold voltage of the memory cell higher than the second level comprises:
applying a third program voltage to the memory cell to alter the threshold voltage of the memory cell;
determining whether the threshold voltage of the memory cell is lower than the second level; and
applying a fourth program voltage to the memory cell to alter the threshold voltage of the memory cell if it has been determined that the threshold voltage of the memory cell is lower than the second level, the fourth program voltage being higher than the third program voltage by a second amount.
2. The method according to claim 1 , wherein the second amount is smaller than the first amount.
3. The method according to claim 1 , wherein the non-volatile semiconductor memory is a NAND type flash memory.
4. The method according to claim 1 , wherein the first value is “0”.
5. The method according to claim 1 , wherein the second value is “0” and the third value is “1”.
6. The method according to claim 1 , the method further comprising maintaining the threshold voltage of the memory cell if the first bit of data is a fourth value, the fourth value differing from the first value.
7. The method according to claim 6 , wherein the fourth value is “1”.
8. The method according to claim 1 , wherein:
the step of making the threshold voltage of the memory cell higher than the second level further comprises determining whether the threshold voltage of the memory cell is lower than a fourth level, before applying the third program voltage, the fourth level being lower than the first level.