Memristive negative differential resistance device
View Patent ↗A memristive Negative Differential Resistance (NDR) device includes a first electrode adjacent to a memristive matrix, the memristive matrix including an intrinsic semiconducting region and a highly doped secondary region, a Metal-Insulator-Transition (MIT) material in series with the memristive matrix, and a second electrode adjacent to the MIT material.
1. A circuit comprising a memristive Negative Differential Resistance (NDR) device comprising:
a first electrode adjacent to a memristive matrix, said memristive matrix comprising an intrinsic semiconducting region and a highly doped secondary region;
a Metal-Insulator-Transition (MIT) material in series with said memristive matrix; and
a second electrode adjacent to said MIT material.
2. The circuit of claim 1 , in which said MIT material comprises at least one of: a vanadium oxide material, a niobium oxide material, an iron oxide material, a manganese oxide material, and a titanium oxide material.
3. The circuit of claim 1 , in which one of: said first electrode and said second electrode is connected to:
a capacitance in parallel with said memristive NDR device; and
a bias voltage supply to apply a bias voltage to said memristive NDR device such that an oscillating signal is produced.
4. The circuit of claim 3 , in which one of said first electrode and said second electrode is connected to a programming voltage supply to change a resistive state of said memristive NDR device by applying a programming voltage to move an interface between said semiconducting region and said highly doped semiconducting region.
5. The circuit of claim 4 , in which a programming voltage from said programming voltage supply changes said resistive state to cause said signal to stop oscillating.
6. The circuit of claim 4 , in which a programming voltage from said programming voltage supply changes said resistive state to cause said signal to start oscillating.
7. The circuit of claim 4 , in which a programming voltage from said programming voltage supply changes said resistive state to cause said oscillating signal to exhibit a target duty cycle.
8. The circuit of claim 4 , in which a programming voltage from said programming voltage supply changes said resistive state to cause said signal to exhibit a target oscillating frequency.
9. The circuit of claim 4 , in which a programming voltage from said programming voltage supply changes said resistive state to cause said signal to exhibit a target amplitude.
10. The circuit of claim 4 , in which said capacitance is one of: a parasitic capacitance and a capacitive device.
11. The circuit of claim 1 , further comprising, a programming voltage supply to change a resistive state of said memristive device.
12. The circuit of claim 11 , in which a programming voltage from said programming voltage supply changes said resistive state to cause said signal to stop oscillating.
13. The circuit of claim 11 , in which a programming voltage from said programming voltage supply changes said resistive state to cause said signal to start oscillating.
14. The circuit of claim 11 , in which a programming voltage from said programming voltage supply changes said resistive state to cause said oscillating signal to exhibit a target duty cycle.
15. The circuit of claim 11 , in which a programming voltage from said programming voltage supply changes said resistive state to cause said signal to exhibit a target oscillating frequency.
16. The circuit of claim 11 , in which a programming voltage from said programming voltage supply changes said resistive state to cause said signal to exhibit a target amplitude.