Method and system for pipelined processing in an integrated embedded image and video accelerator
View Patent ↗A method and system for pipelined processing in an integrated embedded image and video accelerator is described. Aspects of a system for pipelined processing in an integrated embedded image and video accelerator may include circuitry that enables pipeline processing of video data within a single chip, wherein the pipeline processing may further include decoding of a block of video data while simultaneously inverse transforming a previously decoded block of video data. Aspects of the system may also include circuitry that enables transformation, within the single chip, of a block of said video data while simultaneously encoding, within said single chip, a previously transformed block of video data.
1. A method for generating signals in a wireless communication system, the method comprising:
receiving data via an external interface to a single chip;
generating transformed data by performing one or more transform operations on said received data within said single chip;
selectively performing within said single chip:
generating coded data by performing one or more coding operations on said transformed data; and
transmitting said transformed data via said external interface; or
transmitting said coded data via said external interface; and
generating status information associated with the completion of one or both of said one or more transform operations and said one or more coding operations for a specified portion of said received data.
2. The method according to claim 1 , wherein said one or more transform operations comprise a discrete cosine transform operation.
3. The method according to claim 1 , wherein said one or more transform operations comprise an inverse discrete cosine transform operation.
4. The method according to claim 1 , wherein said one or more coding operations comprise run length coding, entropy encoding and/or bit packing operations.
5. The method according to claim 1 , wherein said one or more coding operations comprise run length decoding, entropy decoding and/or bit unpacking operations.
6. The method according to claim 1 , comprising performing said one or more coding operations while concurrently performing said one or more transform operations on subsequent received data.
7. The method according to claim 1 , comprising receiving a data block via said received data, wherein said data block comprises a portion of a data frame.
8. The method according to claim 7 , comprising generating control signals upon completion of said one or more transform operations on said data block.
9. The method according to claim 7 , comprising determining a location of said data block within said data frame.
10. The method according to claim 9 , comprising comparing said location to a specified target block location within said data frame.
11. The method according to claim 10 , comprising generating status information based on said comparing.
12. A system for generating signals in a wireless communication system, the system comprising:
one or more circuits within a single chip, wherein said one or more circuits enable reception of data via an external interface to said single chip;
said one or more circuits enable generation of transformed data by performing one or more transform operations on said received data within said single chip;
said one or more circuits enable selective performing, within said single chip, of:
generation of coded data by performing one or more coding operations on said transformed data; and
transmission of said transformed data via said external interface; or
transmission of said coded data via said external interface; and
said one or more circuits enable generation of status information associated with the completion of one or both of said one or more transform operations and said one or more coding operations for a specified portion of said received data.
13. The system according to claim 12 , wherein said one or more transform operations comprise a discrete cosine transform operation.
14. The system according to claim 12 , wherein said one or more transform operations comprise an inverse discrete cosine transform operation.
15. The system according to claim 12 , wherein said one or more coding operations comprise run length coding, entropy encoding and/or bit packing operations.
16. The system according to claim 12 , wherein said one or more coding operations comprise run length decoding, entropy decoding and/or bit unpacking operations.
17. The system according to claim 12 , wherein said one or more circuits enable performing of said one or more coding operations while concurrently performing said one or more transform operations on subsequent received data.
18. The system according to claim 12 , wherein said one or more circuits enable reception of a data block via said received data, wherein said data block comprises a portion of a data frame.
19. The system according to claim 18 , wherein said one or more circuits enable generation of control signals upon completion of said one or more transform operations on said data block.
20. The system according to claim 18 , wherein said one or more circuits enable determination of a location of said data block within said data frame.
21. The system according to claim 20 , wherein said one or more circuits enable comparing of said location to a specified target block location within said data frame.
22. The system according to claim 21 , wherein said one or more circuits enable generation of status information based on said comparing.