Liquid crystal display and method for manufacturing the same
View Patent ↗A method for manufacturing a liquid crystal display (“LCD”) includes; disposing a gate line including a gate electrode on a substrate, disposing a gate insulating layer on the gate line, disposing a data layer including a data line, source electrode and a drain electrode facing the source electrode on the gate insulating layer, disposing a color filter on the gate insulating layer, disposing an overcoat layer on the color filter, disposing a planarization layer on a portion of the overcoat layer corresponding to the gate line, the data line and the drain electrode, and disposing a pixel electrode in contacted with the overcoat layer in a region corresponding to the color filter.
1. A method for manufacturing a liquid crystal display, the method comprising:
disposing a gate line including a gate electrode on a substrate;
disposing a gate insulating layer on the gate line;
disposing a data line and a drain electrode on the gate insulating layer, wherein the data line includes a source electrode facing the drain electrode;
disposing a color filter on the gate insulating layer;
disposing an overcoat layer on the color filter;
disposing a planarization layer on a portion of the overcoat layer corresponding to the gate line, the data line and the drain electrode; and
disposing a pixel electrode in contact with the overcoat layer in a region corresponding to the color filter.
2. The method of claim 1 , wherein the disposing of the planarization layer comprises:
coating an organic layer on the overcoat layer;
patterning the organic layer and the overcoat layer using a half-tone mask to form a contact hole which exposes the drain electrode, and to reduce a thickness of the organic layer in a region corresponding to the color filter; and
ashing the patterned organic layer.
3. The method of claim 2 , wherein a thickness of the patterned organic layer disposed in the region corresponding to the color filter is in a range of about 0.1 um to about 0.7 um.
4. The method of claim 3 , wherein the ashing is executed in the range of about 2 seconds to about 30 seconds.
5. The method of claim 1 , wherein the forming of the planarization layer comprises:
patterning the overcoat layer through photolithography to form a contact hole which exposes the drain electrode;
coating an organic layer on the overcoat layer; and
removing a portion of the organic layer corresponding to the color filter and a portion of the organic layer corresponding to where the contact hole is formed.
6. The method of claim 1 , further comprising:
disposing a passivation layer between the data layer and the color filter.
7. The method of claim 1 , further comprising:
disposing a light blocking member on the planarization layer.
8. The method of claim 7 , further comprising:
disposing a spacer on the planarization layer after disposing the light blocking member on the planarization layer.