IP Library Granted Patent US 8,482,275
Granted Patent B2
US 8,482,275 · App. 12/840,738 · Granted Jul 9, 2013

Physical quantity detection circuit for allowing precise adjustment of the phase relationship between a sensor signal and a detection signal

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Quick Facts
Patent No.
US 8,482,275
App. No.
12/840,738
Granted
Jul 9, 2013
Kind
B2
Abstract

A PLL circuit generates a plurality of oscillated clocks having different phases. A selector selects one of the plurality of oscillated clocks generated by the PLL circuit. A detection circuit detects a physical quantity signal corresponding to the physical quantity given to a physical quantity sensor from a sensor signal received from the physical quantity sensor based on the oscillated clock selected by the selector.

Claims (16)

1. A physical quantity detection circuit used for a physical quantity sensor that outputs a sensor signal according to a physical quantity given externally, the circuit comprising:

a PLL circuit configured to generate a plurality of oscillated clocks having different phases;

a selector configured to select one of the plurality of oscillated clocks generated by the PLL circuit; and

a detection circuit configured to detect a physical quantity signal corresponding to the physical quantity from the sensor signal based on the oscillated clock selected by the selector,

wherein the PLL circuit includes:

an oscillation circuit including a plurality of delay elements connected in a loop, configured to output the outputs of the plurality of delay elements as the plurality of oscillated clocks,

a low-pass filter configured to generate a control voltage for controlling the delay time of the plurality of delay elements,

a frequency divider configured to divide the frequency of one of the plurality of oscillated clocks to generate a divided clock,

a phase detection circuit configured to detect a phase difference between a reference clock corresponding to the sensor signal and the divided clock, and

a charge pump configured to increase/decrease the control voltage based on the phase difference detected by the phase detection circuit, and

wherein the detection circuit includes:

a frequency division circuit configured to divide the frequency of the oscillated clock selected by the selector, to generate an analog detection signal, and

a sync detection circuit configured to detect the physical quantity signal from the sensor signal using the analog detection signal generated by the frequency division circuit.

2. The physical quantity detection circuit of claim 1 , further comprising:

a phase adjustment circuit, receiving the reference clock and operating in synchronization with an operation clock having a frequency higher than the frequency of the reference clock, configured to output a timing signal once a predetermined number of pulses of the operation clock has been generated after a transition edge of the reference clock,

wherein the frequency division circuit starts generation of the analog detection signal in response to a transition edge of the timing signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →