System for video frame synchronization using sub-frame memories
View Patent ↗A circuit and a method of using the circuit for video frame synchronization are provided. The circuit includes a memory having a capacity less than a full video frame and a “first in first out” (FIFO) interface controlling the memory, further removing the post-read buffer in the memory, and overwriting the post-read buffer in the memory with new data. Some embodiments of the circuit for video frame synchronization provide a wide data bus having a high bandwidth interface to the memory circuit to allow reduced memory clock rate. Some embodiments of the circuit further include a processor that produces a clock signal and measures an input data rate. The processor controls the FIFO interface to generate an output data stream at a preselected frequency, with a preselected phase. More generally, other embodiments of the present invention provide a circuit wherein the processor may be used as a data rate converter and video input timing aberration filter.
1. A circuit for video data conversion comprising:
a video frame synchronizer including a memory circuit having a FIFO interface;
wherein the video frame synchronizer is configured to:
receive input video data having an input data rate and an input data interval associated with an input frame time;
temporarily store the input video data using the memory circuit; and
generate output video data having an output data rate and an output data interval associated with an output frame time;
wherein the memory circuit has a capacity less than a full video frame wherein the capacity is determined based on a difference between the input data interval and the output data interval and a maximum input jitter in the input data interval;
wherein the FIFO interface is configured to retire a post-read buffer in the memory circuit and overwrite the post-read buffer in the memory circuit with new data from the input video data.
2. The circuit of claim 1 further wherein the memory circuit comprises an embedded memory circuit.
3. The circuit of claim 1 further comprising:
a processor that produces a clock signal and measures the input data rate and controls the FIFO interface to generate the output video data at a preselected frequency, with a preselected phase.
4. The circuit of claim 3 wherein the processor serves as a data rate converter and a video input timing aberration filter.
5. The circuit of claim 1 further wherein the capacity is 1/10 th of a full video frame or less.
6. The circuit of claim 1 further comprising:
a wide data bus having a high bandwidth interface to the memory circuit to allow a reduced clock rate for the memory circuit.
7. A method for video frame synchronization comprising:
receiving an input video signal having an input data rate and an input data interval associated with an input frame time;
writing the input video signal into a memory circuit having a FIFO interface;
using the FIFO interface to retire a post-read buffer in the memory circuit, and overwrite the post-read buffer with new data from the input video signal;
using a processor for writing an output video signal having an output data rate and an output data interval associated with an output frame time;
wherein the memory circuit has a capacity less than a full video frame wherein the capacity is determined based on a difference between the input data interval and the output data interval and a maximum input jitter in the input data interval.
8. The method of claim 7 , further wherein the memory circuit comprises an embedded memory circuit.
9. The method of claim 7 , further wherein the capacity is 1/10 th of a full video frame or less.
10. The method of claim 9 , further comprising using the processor to convert the input data rate into the output data rate; and
using the memory circuit for correcting time aberrations or jitter in the input video signal.
11. The circuit of claim 1 , further wherein the input data interval and the output data interval are the same.
12. The circuit of claim 1 , further wherein the capacity is further determined based on a processing latency of the video frame synchronizer.
13. The circuit of claim 5 , further wherein the capacity is 1/20 th of the full video frame or less.
14. The method of claim 7 , further wherein the input data interval and the output data interval are the same.
15. The method of claim 7 , further wherein the capacity is further determined based on a processing latency of the processor.
16. The method of claim 9 , further wherein the capacity is 1/20 th of the full video frame or less.