Redundancy system for non-volatile memory
A redundancy scheme for Non-Volatile Memories (NVM) is described. This redundancy scheme provides means for using defective cells in non-volatile memories to increase yield. The algorithm is based on inverting the program data for data being programmed to a cell grouping when a defective cell is detected in the cell grouping. Defective cells are biased to either “1” or “0” logic states, which are effectively preset to store its biased logic state. A data bit to be stored in a defective cell having a logic state that is complementary to the biased logic state of the cell results in the program data being inverted and programmed. An inversion status bit is programmed to indicate the inverted status of the programmed data. During read out, the inversion status bit causes the stored data to be re-inverted into its original program data states.
1. A non-volatile memory comprising:
n cells for storing an n-bit entry where a defective cell of the n cells is settable to a permanent logic state, where n is an integer value of at least 1;
an inversion status cell programmable from a default first logic state to a second logic state when the n cells store program data inverted relative to input data received by the non-volatile memory; and
a data register for inverting the input data into the program data in response to a mismatch between the permanent logic state of the defective cell and a logic state of a bit of the input data to be programmed to the defective cell, and for inverting read data from the n cells when the inversion status cell stores the second logic state, the data register including:
n register cells corresponding to each of the n cells for storing a bit of the input data and a bit of the read data, each of the n register cells inverting the bit of the input data in response to a program inversion signal and inverting the bit of the read data in response to a read inversion signal; and
an inversion register cell corresponding to the inversion status cell for providing the program inversion signal in response to the mismatch between the permanent logic state of the defective cell and a logic state of a bit of the input data to be programmed to the defective cell.
2. The non-volatile memory of claim 1 , wherein each of the n register cells includes a first latch circuit for storing the bit of the input data, and a second latch circuit for storing the bit of the read data.
3. The non-volatile memory of claim 2 , wherein each of the n register cells includes
a program data inversion circuit for inverting the bit of the input data in response to the program inversion signal.
4. The non-volatile memory of claim 2 , wherein each of the n register cells includes
a read data inversion circuit for inverting the bit of the read data in response to the read inversion signal.
5. The non-volatile memory of claim 2 , wherein each of the n register cells includes
data mismatch comparison logic for comparing the bit of the input data to the bit of the read data to provide a defect signal indicative of the mismatch.
6. The non-volatile memory of claim 1 , wherein the inversion register cell includes a first latch circuit storing by default the second logic state, and a second latch circuit for storing an inversion status bit stored in the inversion status cell.
7. The non-volatile memory of claim 6 , wherein the inversion status register cell provides an output from a sense amplifier coupled to the inversion status cell as the read inversion signal.
8. The non-volatile memory of claim 6 , wherein the inversion status register cell includes
defect detection logic for providing the program inversion signal in response to detecting the second logic state of the inversion status cell or a defect signal indicative of the mismatch between the permanent logic state of the defective cell and a logic state of the bit of the input data to be programmed to the defective cell.
9. The non-volatile memory of claim 8 , wherein the inversion status register cell further includes
a reset circuit for setting the first latch circuit to store the second logic state, and a program data inversion circuit for inverting the bit of the input data in response to the program inversion signal.