Cross OD FinFET patterning

1. A method of forming an integrated circuit structure, the method comprising:

providing a semiconductor substrate;

providing a first lithography mask, a second lithography mask, and a third lithography mask;

forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask;

performing a first etch to form first trenches in the semiconductor substrate to define an active region using the first mask layer;

forming a second mask layer over the semiconductor substrate and over the active region, wherein a pattern of the second mask layer is defined using the second lithography mask, and wherein the second mask layer comprises a plurality of mask strips parallel to each other;

forming a third mask layer over the second mask layer, wherein a pattern of the third mask layer is defined using the third lithography mask, and wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and

performing a second etch to form second trenches in the semiconductor substrate through the opening in the third mask layer.

2. The method of claim 1 , wherein after the step of the second etch, portions of the active region directly underlying the middle portion of the plurality of mask strips form a plurality of fins, and wherein end portions of the active region covered by the third mask layer form source/drain pads on opposite ends of, and forming a continuous region with, the plurality of fins.

3. The method of claim 1 , wherein the first mask layer is a hard mask comprising:

an amorphous carbon layer;

an oxide layer over the amorphous carbon layer; and

an oxynitride layer over the oxide layer.

4. The method of claim 1 , wherein the step of forming the second mask layer comprises:

forming a dummy hard mask layer;

patterning the dummy hard mask layer to generate dummy strips;

forming a spacer layer on top surfaces and sidewalls of the dummy strips;

removing portions of the spacer layer directly over the top surfaces of the dummy strips; and

removing the dummy strips, wherein portions of the spacer layer on the sidewalls of the dummy strips are left un-removed to form the plurality of mask strips.

5. The method of claim 1 , wherein the opening in the third mask layer crosses the plurality of the plurality of mask strips in a top view of the third mask layer.

6. The method of claim 1 further comprising:

after the step of the first etch, filling the first trenches in the semiconductor substrate with a first dielectric material;

before the step of forming the second mask layer, planarizing the first dielectric material;

after the step of the second etch, filling the second trenches in the semiconductor substrate with a second dielectric material;

planarizing the second dielectric material; and

recessing the second dielectric material.

7. The method of claim 6 , wherein the first trenches are deeper than the second trenches.

8. A method of forming an integrated circuit structure, the method comprising:

providing a semiconductor substrate;

performing a first etch to the semiconductor substrate to form first trenches, wherein a portion of the semiconductor substrate defined by the first trenches forms an active region;

filling the first trenches with a first dielectric material;

forming a plurality of mask strips parallel to each other and directly over the active region;

covering end portions of the plurality of mask strips with a mask layer, wherein a middle portion of the plurality of mask strips is not covered by the mask layer;

performing a second etch to the active region to form second trenches using the middle portion of the plurality of mask strips and the mask layer as masks, wherein portions of the active region directly under the middle portion of the plurality of mask strips form a plurality of fins;

filling the second trenches with a second dielectric material;

recessing the second dielectric material to expose sidewalls of the plurality of fins;

forming a gate dielectric layer on top surfaces and the sidewalls of the plurality of fins; and

forming a gate electrode over the gate dielectric layer and directly over the plurality of fins.

9. The method of claim 8 further comprising, before the step of performing the first etch:

forming an additional mask layer over the semiconductor substrate and comprising:

forming an amorphous carbon layer;

forming an oxide layer over the amorphous carbon layer; and

forming an oxynitride layer over the oxide layer; and

patterning the additional mask layer to form patterns for the first trenches.

10. The method of claim 9 further comprising, before the step of filling the first trenches, removing the amorphous carbon layer and the oxide layer, wherein the oxynitride layer remains over the active region.

11. The method of claim 8 , wherein the first trenches have a greater depth than the second trenches.

12. The method of claim 8 , wherein the step of forming the plurality of mask strips comprises:

forming a dummy hard mask layer;

patterning the dummy hard mask layer to generate dummy strips;

forming a spacer layer on top surfaces and sidewalls of the dummy strips;

removing portions of the spacer layer directly over the top surfaces of the dummy strips; and

removing the dummy strips, wherein sidewall portions of the spacer layer on the sidewalls of the dummy strips are left un-removed and form the plurality of mask strips.

13. The method of claim 8 , wherein the mask layer comprises an opening, with the middle portion of the plurality of mask strips exposed through the opening, and wherein the opening crosses the plurality of mask strips in a top view of the mask layer.

14. The method of claim 13 , wherein after the step of the second etch, portions of the active region directly underlying the middle portion of the plurality of mask strips form the plurality of fins, and wherein end portions of the active region covered by the mask layer form source/drain pads on opposite ends of, and forming a continuous region with, the plurality of fins.