SOI-based CMOS imagers employing flash gate/chemisorption processing

1. A method for manufacturing a semiconductor device, comprising the steps of:

providing a silicon-on-insulator substrate including a mechanical substrate, an insulator layer substantially overlying the mechanical substrate, and a seed layer substantially overlying the insulator layer;

growing a semiconductor substrate substantially overlying the seed layer, wherein at least one dopant diffuses into the semiconductor substrate such that, at completion of the growing of the semiconductor substrate, there exists a net dopant concentration profile in the seed layer and the semiconductor substrate which has a minimum value at an interface of the insulator layer and the seed layer and which increases monotonically from the minimum value a predetermined distance within the seed layer and the semiconductor substrate;

removing the mechanical substrate and at least a portion of the insulator layer;

forming an ultrathin oxide layer substantially underlying the semiconductor substrate; and

forming a mono layer of metal substantially underlying the ultrathin oxide layer.

2. The method of claim 1 , wherein the ultrathin oxide layer is formed by a chemisorption process.

3. The method of claim 1 , further comprising the step of depositing an anti-reflective coating substantially underlying the ultrathin oxide layer.

4. The method of claim 1 , further comprising the step of forming at least one CMOS pixel in the semiconductor substrate distal to the insulator layer.

5. The method of claim 4 , wherein the semiconductor substrate is of a first conductivity type and wherein forming at least one CMOS pixel comprises forming at least one CMOS of a second conductivity type in the semiconductor substrate.

6. The method of claim 5 , forming a highly doped sense node of the second conductivity type in the semiconductor substrate.

7. The method of claim 5 , further comprising the step of forming driver logic in the semiconductor substrate.

8. The method of claim 7 , further comprising the step of forming at least one well of the first conductivity type adjacent to and substantially underlying the driver logic.

9. The method of claim 6 , wherein the step of forming at least one CMOS pixel further comprises the steps of:

forming a reset transistor of the second conductivity type in the semiconductor substrate in signal communication with the sense node;

forming a source follower transistor of the second conductivity type in the semiconductor substrate in signal communication with the sense node; and

forming a row select transistor of the second conductivity type in the semiconductor substrate in signal communication with the source follower transistor.

10. The method of claim 9 , wherein the reset transistor, the source follower transistor, and the row select transistor are formed substantially to one side of the at least one CMOS pixel substantially adjacent to the photodiode.

11. The method of claim 9 , wherein the step of forming the at least one CMOS pixel further comprises the steps of:

forming a transfer gate about the sense node; and

forming at least one photodiode about the transfer gate;

wherein the sense node is positioned substantially in the center of the at least one CMOS pixel.

12. The method of claim 11 , wherein the step of forming a transfer gate about the sense node further comprises the step of forming a highly doped n+ region in a highly doped p+ region.

13. The method of claim 11 , wherein the step of forming a transfer gate about the sense node further comprises the step of forming a highly doped p+ region in a highly doped n+ region.

14. The method of claim 10 , further comprising forming an implant about the photodiode configured to step potential in a direction toward the sense node.

15. The method of claim 14 , wherein the implant formed about the photodiode further comprises a buried channel and highly doped region of a first conductivity type adjacent to and formed about the buried channel.