Thin film transistor substrate and the method thereof
View Patent ↗A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
1. A method for manufacturing a thin film transistor array panel, the method comprising:
forming a gate line that includes a gate electrode on an insulation substrate;
forming a gate insulating layer that covers the gate line;
forming a semiconductor layer on the gate insulating layer;
forming a metal layer comprising a first metal layer and a second metal layer on the semiconductor layer such that the second metal layer is on the first metal layer; and
forming a data line and a drain electrode by removing part of the first and second metal layers such that the first metal layer is wider than the second metal layer,
wherein the forming of the data line and the drain electrode comprises forming respective regions of the gate insulating layer to have different thicknesses and exposed upper surfaces by dry etching the first metal layer, the semiconductor layer and a non-stepped portion of the gate insulating layer using a photosensitive film layer as a mask.
2. The method of claim 1 , wherein the forming of the data line and the drain electrode further comprises:
forming a first photosensitive film pattern that has a first portion and a second portion having a thickness higher than that of the first portion on the second metal layer;
simultaneously etching the second metal layer and the first metal layer by using the first photosensitive film pattern as a mask;
etching the semiconductor layer by using the first photosensitive film pattern as the mask;
changing the first photosensitive film pattern into a second photosensitive film pattern by etchback, wherein the photosensitive film is the second photosensitive film;
forming an upper layer of the data line and the drain electrode by wet etching only the second metal layer using the second photosensitive film pattern as the mask; and
wherein the dry etching forms a lower layer of the data line and the drain electrode, and the semiconductor layer.
3. The method of claim 2 further comprises:
forming a passivation layer on the data line and the drain electrode, wherein the passivation layer includes a contact hole for exposing a portion of the drain electrode after the second photosensitive film pattern is removed; and
forming a pixel electrode that is connected to the drain electrode through the contact hole on the passivation layer.
4. The method of claim 2 , wherein the simultaneously etching the second metal layer and the first metal layer performs wet etching by using a nonperoxide-based etchant that includes a fluorine (F) component.
5. The method of claim 2 , wherein the only wet etching the second metal layer performs wet etching by using a nonperoxide-based etchant that does not include a fluorine (F) component.
6. The method of claim 2 , wherein the dry etching the first metal layer, the semiconductor layer and the gate insulating layer that are not covered by the second photosensitive film pattern and is disposed outside the gate electrode is performed until the not covered semiconductor layer is completely removed.
7. The method of claim 2 , wherein the forming the gate line includes forming the gate line having a double layer that includes a lower layer of titanium and an upper layer of copper, and performing wet etching by using the nonperoxide-based etchant that includes the fluorine (F) component.
8. The method of claim 2 , wherein: the forming a lower layer of the data line and the drain electrode, the semiconductor layer, and the gate insulating layer to have different thicknesses by dry etching the first metal layer, the semiconductor layer and the gate insulating layer using the second photosensitive film pattern as the mask further includes removing a titanium oxide layer that is not covered with the second metal layer and disposed on the first metal layer.
9. The method of claim 2 , wherein: the forming a lower layer of the data line and the drain electrode, the semiconductor layer, and the gate insulating layer to have different thicknesses by dry etching the first metal layer, the semiconductor layer and the gate insulating layer using the second photosensitive film pattern as the mask further includes a first step of removing a titanium oxide layer, a second step of etching the first metal layer and the semiconductor layer and a third step of performing post treatment.
10. The method of claim 9 , wherein: the first step of removing the titanium oxide layer uses a gas that includes one of fluorine (F) or SF 6 .
11. The method of claim 10 , wherein: when the titanium oxide layer is removed using a gas including SF 6 and helium (He), the weight ratio of SF6 and helium (He) is 1:0 to 1:5, and the pressure range used in etching is 60 to 400 mT.
12. The method of claim 2 , wherein: the forming a lower layer of the data line and drain electrode, a semiconductor layer, and a gate insulating layer having different thicknesses by dry etching the first metal layer, the semiconductor layer and the gate insulating layer using the second photosensitive film pattern as the mask further includes a first step of removing the titanium oxide film, a second step of removing the first metal layer, a third step of etching the semiconductor layer and a fourth step of performing post treatment.
13. The method of claim 12 , wherein: at the second step, a gas that includes Cl 2 and helium (He) is used, the weight ratio of Cl 2 and helium (He) is 1:0 to 1:5, and the pressure range used in etching is 60 to 200 mT.
14. The method of claim 12 , wherein: the first step of removing the titanium oxide layer uses a gas that includes one of F or SF 6 .
15. The method of claim 14 , wherein: the gas includes SF.sub.6 and helium (He), the weight ratio of SF 6 and helium (He) is 1:0 to 1:5, and the pressure range used in etching is 60 to 400 mT.
16. The method of claim 1 , wherein the semiconductor layer is formed of a first amorphous silicon layer that does not include impurities and a second amorphous silicon layer that is doped with a conductive impurity and disposed on the first amorphous silicon layer, where a channel portion of the thin film transistor is formed by etching the first amorphous silicon layer, and an ohmic contact layer is formed by etching the second amorphous silicon layer.
17. The method of claim 1 , wherein the forming of the data line and the drain electrode further comprises:
forming a first photosensitive film pattern that has a first portion and a second portion that has a thickness higher than that of the first portion on the second metal layer;
simultaneously etching the second metal layer and the first metal layer by using the first photosensitive film pattern as a mask;
changing the first photosensitive film pattern into a second photosensitive film pattern by etchback;
etching the semiconductor layer by using the second photosensitive film pattern as the mask, wherein the photosensitive film is the second photosensitive film;
forming an upper layer of a data line and drain electrode by wet etching only the second metal layer using the second photosensitive film pattern as the mask; and
wherein the dry etching forms a lower layer of the data line and the drain electrode, and the semiconductor layer.
18. The method of claim 1 , wherein the first metal layer has a region that is exposed, and the width of the exposed region of the first metal layer is 15% to 70% of that of the first metal layer.
19. The method of claim 18 , wherein the width of the exposed region of the first metal layer is 0.3 μm to 2.0 μm.
20. The method of claim 1 , wherein the gate insulating layer has a first gate insulating portion that has a first thickness and a second gate insulating portion that has a second thickness that is smaller than the first gate insulating portion.
21. The method of claim 20 , wherein a difference between the first thickness and the second thickness is ⅛ to ¾ of the first thickness.
22. The method of claim 21 , wherein the difference between the first thickness and the second thickness is 500 Å to 3000 Å.
23. The method of claim 20 , wherein the second thickness has a value that is ¼ to ⅞ of the value of the first thickness.
24. The method of claim 20 , wherein the first thickness has a value of 3500 Å to 5000 Å.
25. The method of claim 20 , wherein the second thickness has a value of 500 Å to 4500 Å.
26. The method of claim 1 , wherein the metal layer has a step shaped part.
27. A method for manufacturing a thin film transistor array panel, the method comprising the steps of:
forming a semiconductor layer on a gate insulating layer;
forming a first metal layer and a second metal layer on the semiconductor layer such that the second metal layer is on the first metal layer;
forming a photosensitive film pattern that has a first portion and a second portion having a thickness higher than that of the first portion on the second metal layer;
simultaneously etching the second metal layer and the first metal layer by using the photosensitive film pattern as a mask;
performing one of (1) etching the semiconductor layer by using the photosensitive film pattern as the mask and changing the photosensitive film pattern into a second photosensitive film pattern by etchback or (2) changing the photosensitive film pattern into a second photosensitive film pattern by etchback and etching the semiconductor layer by using the second photosensitive film pattern as the mask;
forming an upper layer of a data line and drain electrode by wet etching the second metal layer using the second photosensitive film pattern as the mask; and
forming a lower layer of the data line and the drain electrode, the semiconductor layer, and the gate insulating layer to have different thicknesses by dry etching the first metal layer, the semiconductor layer and the gate insulating layer using the second photosensitive film pattern as the mask.
28. A method for manufacturing a thin film transistor array panel, the method comprising:
forming a gate line that includes a gate electrode on an insulation substrate;
forming a gate insulating layer that covers the gate line;
forming a semiconductor layer on the gate insulating layer;
forming a first metal layer and a second metal layer on the semiconductor layer such that the second metal layer is on the first metal layer; and
forming a data line, a source electrode and a drain electrode by removing part of the first and second metal layers such that the first metal layer is wider than the second metal layer,
wherein the forming of the data line, the source electrode and the drain electrode comprises forming the semiconductor layer to have a step shaped part by dry etching the first metal layer and the semiconductor layer using a photosensitive film layer as a mask,
wherein the source electrode is located between the step shaped part and the drain electrode.
29. The method of claim 28 , wherein an upper surface of the step shaped part is exposed.