IP Library Granted Patent US 8,373,499
Granted Patent B2
US 8,373,499 · App. 12/844,450 · Granted Feb 12, 2013

Semiconductor integrated circuit having normal mode and self-refresh mode

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Quick Facts
Patent No.
US 8,373,499
App. No.
12/844,450
Granted
Feb 12, 2013
Kind
B2
Abstract

An SDRAM includes a DC-DC converter IC for generating a first internal power supply voltage from external power supply voltage, a regulator IC for generating a second internal power supply voltage lower than the first internal power supply voltage, from external power supply voltage, and a switching portion for supplying the first internal power supply voltage to an internal circuit in a normal operation mode and supplying the second internal power supply voltage to the internal circuit in a self-refresh mode. The switching unit allows the DC-DC converter IC and the regulator IC to operate simultaneously only for a prescribed overlapped period, at a time of operation mode switching. The DC-DC converter IC temporarily increases the first internal power supply voltage within the operating voltage range of the internal circuit in the overlapped period.

Claims (19)

1. A semiconductor integrated circuit having a normal operation mode and a self-refresh mode, comprising:

a first internal step-down circuit which generates a first internal power supply voltage from a supplied external power supply voltage;

a second internal step-down circuit which generates a second internal power supply voltage lower than said first internal power supply voltage, from the supplied external power supply voltage; and

a switching unit which supplies said first internal power supply voltage output from said first internal step-down circuit to an internal circuit in said normal operation mode and supplies said second internal power supply voltage output from said second internal step-down circuit to said internal circuit in said self-refresh mode,

wherein

at a time of operation mode switching from said normal operation mode to said self-refresh mode, said switching unit activates said second internal step-down circuit at a timing earlier than a switching timing of operation mode and stops said first internal step-down circuit at said switching timing, and

at a time of operation mode switching from said self-refresh mode to said normal operation mode, said switching unit activates said first internal step-down circuit at a switching timing of operation mode and stops said second internal step-down circuit at a timing later than said switching timing.

2. The semiconductor integrated circuit according to claim 1 , wherein

said internal circuit has a prescribed operating voltage range,

at the time of operation mode switching from said normal operation mode to said self-refresh mode, said first internal step-down circuit temporarily increases said first internal power supply voltage within said prescribed operating voltage range, in a period from a timing earlier than the timing of activating said second internal step-down circuit to the switching timing of operation mode, and

at the time of operation mode switching from said self-refresh mode to said normal operation mode, said first internal step-down circuit temporarily increases said first internal power supply voltage within said prescribed voltage range, in a period from the switching timing of operation mode to a timing later than the timing of stopping said second internal step-down circuit.

3. A semiconductor integrated circuit having a normal operation mode and a self-refresh mode, comprising:

a first internal step-down circuit which generates a first internal power supply voltage from a supplied external power supply voltage;

a second internal step-down circuit which generates a second internal power supply voltage lower than said first internal power supply voltage, from the supplied external power supply voltage; and

a switching unit which supplies said first internal power supply voltage output from said first internal step-down circuit to an internal circuit in said normal operation mode and supplies said second internal power supply voltage output from said second internal step-down circuit to said internal circuit in said self-refresh mode,

wherein

said first internal step-down circuit is a DC-DC converter which converts the external power supply voltage to generate said first internal power supply voltage by controlling switching of a first transistor and a second transistor, and

said second internal step-down circuit is a series regulator which converts the external power supply voltage to generate said second internal power supply voltage by controlling base current of a third transistor.

4. The semiconductor integrated circuit according to claim 3 , wherein the first internal step-down circuit and the second internal step-down circuit are capable of simultaneously operating in a prescribed overlapped period.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE INCORRECT PATENT NUMBER 13/446,454, AND REPLACE WITH 13/466,454 PREVIOUSLY RECORDED ON REEL 032467 FRAME 0095. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF ASSIGNORS INTEREST. Recorded Apr 3, 2014
From: SANYO ELECTRIC CO., LTD.
To: XACTI CORPORATION
Reel/Frame 032601/0646 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2014
From: SANYO ELECTRIC CO., LTD.
To: XACTI CORPORATION
Reel/Frame 032467/0095 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2010
From: MORIGUCHI, KOJI; TAKAHASHI, TOSHIO
To: SANYO ELECTRIC CO., LTD.
Reel/Frame 024748/0042 →