Systems and methods for partitioned color, double rate video transfer

1. A laser diode driver (LDD), comprising:

a first digital-to-analog converted (DAC) configured to receive a first color data word and produce, in dependence on the first color data word, a first output current to drive a light source of a first color;

a second DAC configured to receive a second color data word and produce, in dependence on the second color data word, a second output current to drive a light source of a second color;

a third DAC configured to receive a third color data word and produce, in dependence on the third color data word, a third output current to drive a light source of a third color; and

interface circuitry configured to

receive a data transfer clock signal, wherein each cycle of the data transfer clock signal includes a low-to-high portion and a high-to-low portion;

receive and store a first transfer word in response to the low-to-high portion of a cycle of the data transfer clock signal;

receive and store a second transfer word in response to the high-to-low portion of a cycle of the data transfer clock signal;

produce the first color data word, the second color data word and the third color data word in dependence on the first and second stored transfer words; and

drive the first DAC with the first color data word;

drive the second DAC with second color data word; and

drive the third DAC with the third color data.

2. The LDD of claim 1 , wherein:

the first color data word comprises a first M-bit word;

the second color data word comprises a second M-bit word;

the third color data word comprises a third M-bit word;

the first transfer word comprises a first (3*M)/2 bit word; and

the second transfer word comprises a second (3*M)/2 bit word.

3. The LDD of claim 2 , wherein:

M=10; and

(3*M)/2=15.

4. The LDD of claim 1 , wherein:

the first color is red;

the second color is blue; and

the third color is green.

5. The LDD of claim 1 , wherein:

one of the first and second transfer words stored by the interface circuitry during a cycle of the data transfer clock signal includes

all bits of the first color data word, and

some bits of the second color data word; and

the other one of the first and second transfer words stored by the interface circuitry during a cycle of the data transfer clock signal includes

all bits of the third color data word, and

the remaining bits of the second color data word.

6. The LDD of claim 1 , wherein:

one of the first and second transfer words stored by the interface circuitry during a cycle of the data transfer clock signal includes

some bits of the first color data word,

some bits of the second color data word, and

some bits of the third color data word; and

the other one of the first and second transfer words stored by the interface circuitry during a cycle of the data transfer clock signal includes

the remaining bits of the first color data word,

the remaining bits of the second color data word, and

the remaining bits of the third color data word.

7. The LDD of claim 1 , wherein the interface circuitry includes:

input data latches configured to

latch and thereby store the first transfer word in response to the low-to-high portion of a cycle of the data transfer clock signal; and

latch and thereby store the second transfer word in response to the high-to-low portion of a cycle of the data transfer clock signal;

multiplexers configured to produce the first color data word, the second color data word and the third color data word in dependence on the first and second received transfer words; and

output data latches configured to

latch the first color data word, the second color data word and the third color data word from the multiplexers;

drive the first DAC with the first color data word;

drive the second DAC with the second color data word; and

drive the third DAC with the third color data word.

8. A method for use with a laser diode driver (LDD), that includes

a first digital-to-analog converted (DAC) configured to receive a first color data word and produce, in dependence on the first color data word, a first output current to drive a light source of a first color,

a second DAC configured to receive a second color data word and produce, in dependence on the second color data word, a second output current to drive a light source of a second color, and

a third DAC configured to receive a third color data word and produce, in dependence on the third color data word, a third output current to drive a light source of a third color,

the method comprising:

receiving a data transfer clock signal, wherein each cycle of the data transfer clock signal includes a low-to-high portion and a high-to-low portion;

receiving and storing a first transfer word in response to the low-to-high portion of a cycle of the data transfer clock signal;

receiving and storing a second transfer word in response to the high-to-low portion of a cycle of the data transfer clock signal;

producing the first color data word, the second color data word and the third color data word in dependence on the first and second received transfer words;

driving the first DAC with the first color data word;

driving the second DAC with the second color data word; and

driving the third DAC with the third color data word.

9. The method of claim 8 , wherein:

the first color data word comprises a first M-bit word;

the second color data word comprises a second M-bit word;

the third color data word comprises a third M-bit word;

the first transfer word comprises a first (3*M)/2 bit word; and

the second transfer word comprises a second (3*M)/2 bit word.

10. The method of claim 9 , wherein:

M=10; and

(3*M)/2=15.

11. The method of claim 8 , wherein:

the first color is red;

the second color is blue; and

the third color is green.

12. The method of claim 8 , wherein:

the step of receiving and storing the first transfer word in response to the low-to-high portion of a cycle of the data transfer clock signal includes receiving and storing

all bits of the first color data word, and

some bits of the second color data word; and

the step of receiving and storing the second transfer word in response to the high-to-low portion of a cycle of the data transfer clock signal includes receiving and storing

all bits of the third color data word, and

the remaining bits of the second color data word.

13. The method of claim 8 , wherein:

the step of receiving and storing the first transfer word in response to the low-to-high portion of a cycle of the data transfer clock signal includes receiving and storing

some bits of the first color data word,

some bits of the second color data word, and

some bits of the third color data word; and

the step of receiving and storing the second transfer word in response to the high-to-low portion of a cycle of the data transfer clock signal includes receiving and storing

the remaining bits of the first color data word,

the remaining bits of the second color data word, and

the remaining bits of the third color data word.

14. The method of claim 8 , further comprising:

driving a light source of the first color with the first output current produced by the first DAC;

driving a light source of the second color with the second output current produced by the second DAC; and

driving a light source of the third color with the third output current produced by the third DAC.

15. A system, comprising:

a controller configured

accept an input video signal that includes first color data, second color data, and third color data per pixel;

produce a first transfer word and a second transfer word in dependence on the first color data, the second color data, and the third color data per pixel;

transmit the first transfer word to a laser diode driver (LDD) over a multi-bit wide bus during a first portion of one cycle of a data transfer clock signal; and

transmit the second transfer word to the LDD over the same multi-bit wide bus during a second portion of the same one cycle of the data transfer clock.

16. The system of claim 15 , wherein

the first color data, the second color data, and the third color data per pixel comprises M-bits of first color data, M-bits of second color data, and M-bits of third color data per pixel; and

the first transfer word comprises a first (3*M)/2 bit word;

the second transfer word comprises a second (3*M)/2 bit word; and

the controller is configured to transmit the first and second (3*M)/2 bit words to the LDD over the same (3*M)/2 bit wide bus during one cycle of the data transfer clock signal.

17. The system of claim 15 , wherein the controller includes latches configured to produce the first transfer word and the second transfer word in dependence on the first color data, the second color data, and the third color data per pixel.

18. The system of claim 15 , wherein the controller is also configured to perform at least one of scaling and pre-distortion of the input video signal such that color data within the first transfer word and the second transfer word has already been scaled and/or pre-distorted.

19. A system, comprising:

a controller configured to

accept an input video signal that includes first color data, second color data, and third color data per pixel;

produce a first transfer word and a second transfer word in dependence on the first color data, the second color data, and the third color data per pixel; and

transmit the first transfer word and the second transfer word to a laser diode driver (LDD) over a same multi-bit wide bus during one cycle of a data transfer clock signal; and

a laser diode driver (LDD) configured to

receive the data transfer clock signal, wherein each cycle of the data transfer clock signal includes a low-to-high portion and a high-to-low portion;

receive and store the first transfer word in response to the low-to-high portion of a cycle of the data transfer clock signal;

receive and store the second transfer word in response to the high-to-low portion of a cycle of the data transfer clock signal;

produce the first color data, the second color data and the third color data in dependence on the first and second received transfer words; and

drive a first DAC of the LDD with the first color data;

drive a second DAC of the LDD with the second color data; and

drive a third DAC of the LDD with third color data.

20. The system of claim 19 , further comprising:

a red light emitting element;

a green light emitting element; and

a blue light emitting element;

wherein each of the red, green and blue light emitting elements is driven by a current output of a different one of the first, second and third DACs.

21. The system of claim 20 , wherein each of the red, green and blue light emitting elements comprises a three separate laser diodes or three separate light emitting diodes.

22. A method, comprising:

accepting an input video signal that includes first color data, second color data, and third color data per pixel;

producing a first transfer word and a second transfer word in dependence on the first color data, the second color data, and the third color data per pixel;

transmitting the first transfer word to a laser diode driver (LDD) over a multi-bit wide bus during a first portion of one cycle of a data transfer clock signal; and

transmitting the second transfer word to the LDD over the same multi-bit wide bus during a second portion of the same one cycle of the data transfer clock.

23. A method, comprising:

accepting an input video signal that includes first color data, second color data, and third color data per pixel;

producing a first transfer word and a second transfer word in dependence on the first color data, the second color data, and the third color data per pixel; and

transmitting the first transfer word and the second transfer word to a laser diode driver (LDD) over a same multi-bit wide bus during one cycle of a data transfer clock signal;

wherein the first color data, the second color data, and the third color data per pixel comprise, respectively, M-bits of first color data, M-bits of second color data, and M-bits of third color data per pixel; and

wherein the first transfer word comprises a first (3*M)/2 bit word;

wherein the second transfer word comprises a second (3*M)/2 bit word; and

wherein the transmitting comprises transmitting the first and second (3*M)/2 bit words to the LDD over the same (3*M)/2 bit wide bus during one cycle of the data transfer clock signal.

24. The system of claim 15 , wherein:

one of the first and second transfer words includes

all bits of the first color data word, and

some bits of the second color data word; and

the other one of the first and second transfer words includes

all bits of the third color data word, and

the remaining bits of the second color data word.

25. The system of claim 15 , wherein:

one of the first and second transfer words includes

some bits of the first color data word,

some bits of the second color data word, and

some bits of the third color data word; and

the other one of the first and second transfer words includes

the remaining bits of the first color data word,

the remaining bits of the second color data word, and

the remaining bits of the third color data word.