IP Library Granted Patent US 8,604,606
Granted Patent B2
US 8,604,606 · App. 12/845,299 · Granted Dec 10, 2013

Heat sink package

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Quick Facts
Patent No.
US 8,604,606
App. No.
12/845,299
Granted
Dec 10, 2013
Kind
B2
Abstract

Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. The heat sink package includes a heat sink having a cavity on an upper surface thereof; a metal layer formed on the bottom surface of the cavity; a solder paste layer formed on the metal layer; a substrate on the solder paste layer; and a lead and a semiconductor chip mounted on the substrate.

Claims (30)

1. A heat sink package comprising:

a heat sink having a cavity on an upper surface thereof;

an insulating anodized layer formed on the bottom surface of the cavity;

a metal layer pattern contacting the anodized layer; and

a lead and a semiconductor chip, each mounted on the metal layer pattern.

2. The heat sink package of claim 1 , wherein the heat sink comprises aluminum and the anodized layer comprises Al2O3.

3. The heat sink package of claim 1 , wherein the anodized layer, the metal layer pattern and the semiconductor chip are arranged in the cavity.

4. The heat sink package of claim 1 , wherein the cavity has a depth greater than the sum of a height of the anodized layer, a height of the metal layer pattern, and a height of the semiconductor chip.

5. The heat sink package of claim 1 , further comprising an epoxy resin filling in the cavity in order to protect the anodized layer, the metal layer pattern and the semiconductor chip.

6. The heat sink package of claim 5 , wherein the lead extends from the metal layer pattern toward the outside of the epoxy resin.

7. A heat sink package comprising:

a heat sink having a cavity on an upper surface thereof;

an insulating anodized layer formed on the bottom surface of the cavity;

a metal layer pattern contacting the anodized layer;

a lead and a semiconductor chip, each mounted on the metal layer pattern;

wherein the anodized layer, the metal layer pattern and the semiconductor chip are arranged in the cavity having a depth greater than the sum of a height of the anodized layer, a height of the metal layer pattern, and a height of the semiconductor chip.

8. The heat sink package of claim 7 , further comprising an epoxy resin filling in the cavity in order to protect the anodized layer, the metal layer pattern and the semiconductor chip.

9. The heat sink package of claim 8 , wherein the lead extends from the metal layer pattern toward the outside of the epoxy resin.

10. A heat sink package comprising:

a heat sink having a cavity on an upper surface thereof;

an insulating anodized layer formed on the bottom surface of the cavity;

a metal layer pattern on the anodized layer;

two or more semiconductor chips, each chip having a plurality of terminal, said terminals electrically connected the metal layer pattern, and

one or more leads mounted on the metal layer pattern and extending from the metal layer pattern and beyond cavity.

11. The heat sink package of claim 10 , wherein the heat sink comprises aluminum and the anodized layer comprises Al2O3.

12. The heat sink package of claim 10 , wherein the anodized layer, the metal layer pattern and the semiconductor chips are arranged in the cavity.

13. The heat sink package of claim 10 , wherein the cavity has a depth greater than the sum of a height of the anodized layer, a height of the metal layer pattern, and a height of the tallest semiconductor chip.

14. The heat sink package of claim 10 , further comprising an epoxy resin filling in the cavity in order to protect the anodized layer, the metal layer pattern and the semiconductor chips.

15. The heat sink package of claim 14 , wherein the lead extends from the metal layer pattern toward the outside of the epoxy resin.

16. The heat sink package of claim 10 wherein bond wires electrically connect the terminals of the semiconductor chips to the metal layer pattern.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 04481, FRAME 0541 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0459 →
PATENT SECURITY AGREEMENT Recorded Nov 17, 2017
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 044481/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2017
From: FAIRCHILD KOREA SEMICONDUCTOR, LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 044361/0205 →