Nonvolatile memory cell with well extending under transistor and data storage capacitor of memory cell

1. A memory device, comprising:

a capacitor having a first capacitor plate and a second capacitor plate, wherein the first and second capacitor plates are separated by an insulating layer and are formed over a first portion of a semiconductor substrate;

a transistor having a source region, a drain region, and a gate region, the gate region being coupled to the second capacitor plate; wherein the transistor is formed over a second portion of the semiconductor substrate; and

a well region disposed in the first and second portions of the semiconductor substrate and extending continuously between the first and second portions of the semiconductor substrate, wherein the well region has a doping-type that is opposite a doping-type of the semiconductor substrate.

2. The memory device of claim 1 , further comprising:

control circuitry configured to store a first data value in the memory cell by applying a voltage difference across the control gate and the well region, wherein the control gate receives a higher voltage than the well region while the voltage difference is applied to store the first data value; and

wherein the control circuitry is further configured to store a second data value in the memory cell by applying the voltage difference across the control gate and the well region, wherein the control gate receives a lower voltage than the well region while the voltage difference is applied to store the second data value.

3. The memory cell of claim 1 , wherein the well region extends in the substrate under at least substantially the entire surface area of first capacitor plate.

4. The memory cell of claim 1 , wherein the insulating layer of the capacitor comprises

a first oxide layer proximate to the first capacitor plate;

a second oxide layer proximate to the second capacitor plate; and

a nitride layer sandwiched between the first and second oxide layers.

5. The memory cell of claim 1 , further comprising:

a guard ring that at least partially laterally surrounds at least one of the first or second capacitor plates.

6. The memory cell of claim 1 , further comprising:

a metal shield layer extending at least substantially over the first and second capacitor plates and over the gate region of the transistor.

7. The memory cell of claim 6 , further comprising:

at least one via coupling the metal shield layer to the first capacitor plate.

8. The memory cell of claim 7 , further comprising:

a guard ring coupled to the metal shield layer and which at least partially laterally surrounds at least one of the first or second capacitor plates.

9. The memory cell of claim 1 , wherein the first and second capacitor plates and the gate region comprise polysilicon.

10. A method of accessing an EEPROM memory cell, comprising:

writing a first data state to the EEPROM memory cell by applying a voltage difference of greater than 10 volts across a capacitor of the EEPROM memory cell, wherein a control gate of the EEPROM cell receives a higher voltage than a well region of the EEPROM cell while the voltage difference is applied to store the first data value; and

writing a second data state to the EEPROM memory cell by applying the voltage difference across the capacitor of the EEPROM cell, wherein the control gate of the EEPROM cell receives a lower voltage than the well region of the EEPROM cell while the voltage difference is applied to store the second data value.

11. The method of claim 10 , further comprising:

reading a data state from the EEPROM memory cell by voltage or current sensing the stored charge/potential on the floating gate region of the transistor of the EEPROM memory cell.

12. A method of accessing an EEPROM memory cell, comprising:

writing a first data state to the EEPROM memory cell by driving a control gate of the EEPROM cell to a first voltage and concurrently driving both a substrate and a well under the control gate to a second voltage, where the second voltage is less than the first voltage;

writing a second data state to the EEPROM memory cell by driving the control gate of the EEPROM cell to the second voltage and concurrently driving both the substrate and the well under the control gate to the first voltage, where the second data state is different from the first data state;

wherein a difference between the first and second voltages is greater than approximately 10 volts.