Method for fabrication of a semiconductor device and structure
View Patent ↗A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.
1. A method of manufacturing a semiconductor wafer, the method comprising:
providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks;
transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and
performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.
2. The method according to claim 1 wherein:
said monocrystalline layer further comprises transistors formed therein.
3. The method according to claim 1 wherein said transferring comprises:
performing layer transfer of said monocrystalline layer to a carrier; and
performing layer transfer of said monocrystalline layer on top of said metal layers from said carrier.
4. The method according to claim 1 , further comprising:
etching said monocrystalline layer to form a plurality of planar transistors.
5. The method according to claim 1 , further comprising:
etching said monocrystalline layer to form a plurality of p-type and n-type transistors.
6. The method according to claim 1 , further comprising:
optical annealing of at least one region of said monocrystalline layer.
7. The method according to claim 1 , wherein:
said monocrystalline layer comprises a repeating pattern.
8. A method of manufacturing a semiconductor wafer, the method comprising:
providing a base wafer comprising a semiconductor substrate, metal layers, and first alignment marks;
preparing a monocrystalline layer comprising semiconductor regions comprising partially-formed transistors, and second alignment marks;
performing layer transfer of said monocrystalline layer on top of said metal layers; and
finalizing forming said transistors after said layer transfer.
9. The method according to claim 8 further comprises:
performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.
10. The method according to claim 8 , wherein said transfer comprises:
performing layer transfer of said monocrystalline layer to a carrier; and
performing layer transfer of said monocrystalline layer on top of said metal layers from said carrier.
11. The method according to claim 8 wherein said transistors are planar transistors.
12. The method according to claim 8 , further comprising:
optical annealing of at least one region of said monocrystalline layer.
13. The method according to claim 8 , wherein
said transistors are of p-type or n-type transistors.
14. A method of manufacturing a semiconductor wafer, the method comprising:
providing a base wafer comprising a semiconductor substrate, metal layers, and first alignment marks;
preparing a monocrystalline layer comprising semiconductor regions, and second alignment marks;
performing layer transfer of said monocrystalline layer, first to a carrier and then on top of said metal layers; and
etching said monocrystalline layer to define individual transistors.
15. The method according to claim 14 , further comprising:
performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.
16. The method according to claim 14 , wherein said monocrystalline layer comprises partially formed transistors.
17. The method according to claim 14 , wherein said monocrystalline layer comprises a repeating pattern.
18. The method according to claim 14 , wherein said transistors are planar transistors.
19. The method according to claim 14 , wherein said transistors comprise p-type transistors and n-type transistors.
20. The method according to claim 14 , further comprising:
optical annealing of at least one region of said monocrystalline layer.