Secure data entry device
View Patent ↗A secure data entry device including a housing, tamper sensitive circuitry located within the housing and tampering alarm indication circuitry arranged to provide an alarm indication in response to attempted access to the tamper sensitive circuitry, the tampering alarm indication circuitry including at least one conductor, a signal generator operative to transmit a signal along the at least one conductor and a signal analyzer operative to receive the signal transmitted along the at least one conductor and to sense tampering with the at least one conductor, the signal analyzer being operative to sense the tampering by sensing changes in at least one of a rise time and a fall time of the signal.
1. A secure data entry device comprising:
a housing;
a protective enclosure located within said housing;
tamper sensitive circuitry located within said protective enclosure; and
tampering alarm indication circuitry arranged to provide an alarm indication in response to attempted access to said tamper sensitive circuitry, at least part of said tampering alarm indication circuitry being located within said protective enclosure, said tampering alarm indication circuitry comprising:
at least one conductor forming part of said protective enclosure;
a signal generator operative continuously, whether or not the secure data entry device is operative as a secured keypad device, to transmit a signal along said at least one conductor; and
a signal analyzer operative to receive said signal transmitted along said at least one conductor and to sense tampering with said at least one conductor, said signal analyzer being operative to sense said tampering by sensing changes in at least one of a rise time and a fall time of said signal, said at least one of said rise time and said fall time being less than a time normally required for said signal to traverse said at least one conductor.
2. A secure data entry device according to claim 1 and wherein said at least one of said rise time and said fall time is less than one hundredth of said time normally required for said signal to traverse said conductor.
3. A secure data entry device according to claim 1 and wherein said signal analyzer compares a reference signal with said signal transmitted along said conductor.
4. A secure data entry device according to claim 3 and wherein said signal analyzer also comprises a reference signal memory.
5. A secure data entry device according to claim 4 and wherein said signal analyzer comprises an analog-to-digital converter and a digital signal comparator.
6. A secure data entry device according to claim 5 and wherein:
said reference signal is a Fast Fourier Transform (FFT) reference signal; and
said signal analyzer also comprises a processor including FFT calculation functionality.
7. A secure data entry device according to claim 4 and wherein said signal analyzer comprises a digital-to-analog converter and an analog comparator.
8. A secure data entry device according to claim 1 and wherein said signal generator is also operative to provide a signal timing input to said signal analyzer.
9. A secure data entry device according to claim 1 and wherein said at least one conductor comprises a pair of conductors running in parallel to each other.
10. A secure data entry device according to claim 9 and wherein one of said pair of conductors is grounded.
11. A secure data entry device according to claim 1 and wherein said at least one conductor is routed parallel to a ground plate.
12. A secure data entry device according to claim 1 and wherein said at least one conductor comprises multiple conductors of different lengths.
13. A secure data entry device according to claim 1 and wherein said at least one conductor is formed on a printed circuit substrate.
14. A secure data entry device according to claim 1 and wherein said at least one conductor forms part of at least one of an integrated circuit and a hybrid circuit.
15. A secure data entry device according to claim 1 and wherein said signal generator and said signal analyzer are located within a protective enclosure defined within a secure integrated circuit.