Method for fabrication of a semiconductor device and structure

1. A semiconductor device comprising:

a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials;

a second single crystal silicon layer overlying said at least one metal layer, wherein said second single crystal silicon layer comprises:

through vias through said second single crystal silicon layer; and

a plurality of second transistors arranged in substantially parallel bands wherein each of a plurality of the bands comprises a portion of said second transistors along an axis in a repeating pattern; and

connection paths between a portion of said first transistors and second transistors,

wherein each of said connection paths comprises a first metal strip substantially parallel to said axis, and a second metal strip substantially perpendicular to said axis,

wherein said first metal strip is on top of said second single crystal silicon layer,

wherein said second metal strip is underneath said second single crystal silicon layer, and

wherein said first metal strip and said second metal strip provide or are capable of providing a contact area through one of said through vias.

2. A semiconductor device according to claim 1 , wherein said second single crystal silicon layer is less than 0.4 micron thick.

3. A semiconductor device according to claim 1 , wherein said second transistors are planar transistors.

4. A semiconductor device according to claim 1 , wherein said second single crystal silicon layer further comprises second alignment marks, wherein said through vias are aligned in a first direction to said first alignment marks and aligned in a second direction to said second alignment marks.

5. A semiconductor device according to claim 1 , wherein said second transistors are gate-last transistors.

6. A semiconductor device comprising:

a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying said first single crystal silicon layer, wherein said metal layers comprises copper or aluminum more than other materials;

an overlying second single crystal silicon layer comprising second transistors, second alignment marks, and through vias through said second single crystal silicon layer, said through vias aligned in a first direction to said first alignment marks and in a second direction to said second alignment marks;

connection paths between a portion of said first transistors and second transistors,

wherein each of said connection paths comprises a first metal strip substantially parallel to an axis, and a second metal strip substantially perpendicular to said axis,

wherein said first metal strip is on top of said second single crystal silicon layer;

wherein said second metal strip is underneath said second single crystal silicon layer, and

wherein said first metal strip and second metal strip provide or are capable of providing a contact area through one of said through vias.

7. A semiconductor device according to claim 6 , wherein said second single crystal silicon layer is less than 0.4 micron thick.

8. A semiconductor device according to claim 6 , wherein said second transistors are planar transistors.

9. A semiconductor device according to claim 6 , wherein said second transistors are gate-last transistors.

10. A semiconductor device comprising:

a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials;

a second single crystal silicon layer overlying said at least one metal layer;

wherein said second single crystal silicon layer comprises through vias through said second single crystal silicon layer and a plurality of second transistors comprising P type transistors and N type transistors;

wherein said second transistors are arranged in substantially parallel bands, and

wherein each of a plurality of the bands comprises a portion of said second transistors along an axis in a repeating pattern;

connection paths between a portion of said first transistors and second transistors,

wherein each of said connection paths comprises a first metal strip substantially parallel to said axis, and a second metal strip substantially perpendicular to said axis,

wherein said first metal strip is on top of said second single crystal silicon layer,

wherein said second metal strip is underneath said second single crystal silicon layer, and

wherein said first metal strip and second metal strip provide or are capable of providing a contact area through one of said through vias.

11. A semiconductor device according to claim 10 , wherein said second single crystal silicon layer is less than 0.4 micron thick.

12. A semiconductor device according to claim 10 , wherein said second transistors are planar transistors.

13. A semiconductor device according to claim 10 ,

wherein said second single crystal silicon layer comprises second alignment marks, and wherein said through vias are aligned in a first direction to said first alignment marks and in a second direction to said second alignment marks.

14. A semiconductor device according to claim 10 , wherein said second transistors are gate-last transistors.