IP Library Granted Patent US 8,218,358
Granted Patent B2
US 8,218,358 · App. 12/851,054 · Granted Jul 10, 2012

Nonvolatile semiconductor memory device and method for driving same

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,218,358
App. No.
12/851,054
Granted
Jul 10, 2012
Kind
B2
Abstract

According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.

Claims (36)

1. A nonvolatile semiconductor memory device, comprising:

a substrate;

a stacked body provided on the substrate, the stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, a through-hole being made in the stacked body to align in a stacking direction;

a semiconductor pillar buried in an interior of the through-hole;

a charge storage film provided between the electrode film and the semiconductor pillar; and

a drive circuit supplying a potential to the electrode film,

a diameter of the through-hole differing by a position in the stacking direction,

the drive circuit supplying a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.

2. The device according to claim 1 , wherein a diameter of the through-hole decreases toward the substrate.

3. The device according to claim 2 , wherein the through-holes are made collectively by dry etching.

4. The device according to claim 1 , wherein

the stacked body includes a plurality of partial stacked bodies arranged in the stacking direction, a plurality of the insulating films and a plurality of the electrode films being disposed in the partial stacked body, and

in each of the partial stacked bodies, a diameter of the through-hole decreases toward the substrate.

5. The device according to claim 4 , wherein portions of the through-holes made in each of the partial stacked bodies are made collectively for the partial stacked body by dry etching.

6. The device according to claim 1 , wherein

the through-hole has a circular configuration as viewed from the stacking direction, and

a potential provided by the drive circuit to one of the electrode films is determined according to

V= 6999.4 ×r 3 −1971.3 ×r 2 +194.66 ×r− 5.0952

where r (μm) is a diameter of a portion of the through-hole piercing the one electrode film, V is a potential difference between the one electrode film and the semiconductor pillar, and V is a relative potential difference having a potential difference of 1 when the diameter is 0.06 μm.

7. The device according to claim 1 , wherein the drive circuit includes:

a decoder to output a control signal;

a pump circuit to increase a supplied potential; and

a switch element to switch between connecting and disconnecting the pump circuit and the electrode film based on the control signal.

8. The device according to claim 7 , wherein the pump circuit and the switch element are provided for each of the electrode films.

9. The device according to claim 1 , further comprising:

a back gate disposed between the substrate and the stacked body; and

a connection member provided in the back gate to connect two adjacent semiconductor pillars to each other.

10. The device according to claim 1 , wherein a memory cell region and a peripheral circuit region are set in the substrate, the semiconductor pillar and the charge storage film are disposed in the memory cell region, and the drive circuit is disposed in the peripheral circuit region.

11. A method for driving a nonvolatile semiconductor memory device, the device including: a substrate; a stacked body provided on the substrate, the stacked body including a plurality of insulating films alternately stacked with a plurality of electrode films, a through-hole being made in the stacked body to align in a stacking direction; a semiconductor pillar buried in an interior of the through-hole; and a charge storage film provided between the electrode film and the semiconductor pillar, a diameter of the through-hole differing by a position in the stacking direction, the method comprising:

when applying a potential to the electrode film, supplying a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.

12. The method according to claim 11 , comprising providing a potential to one of the electrode films, the potential being determined according to

V= 6999.4 ×r 3 −1971.3 ×r 2 +194.66 ×r− 5.0952

where r (μm) is a diameter of a portion of the through-hole piercing the one electrode film, V is a potential difference between the one electrode film and the semiconductor pillar, and V is a relative potential difference having a potential difference of 1 when the diameter is 0.06 μm,

the through-hole having a circular configuration as viewed from the stacking direction.

13. The method according to claim 11 , wherein the potential is a writing potential to inject an electron from the semiconductor pillar into the charge storage film.

14. The method according to claim 11 , wherein the potential is a reading potential to detect whether or not an electron is stored in the charge storage film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2010
From: KATSUMATA, RYOTA; AOCHI, HIDEAKI; TANAKA, HIROYASU; KITO, MASARU; FUKUZUMI, YOSHIAKI; KIDOH, MASARU; KOMORI, YOSUKE; ISHIDUKI, MEGUMI; MATSUNAMI, JUNYA; FUJIWARA, TOMOKO; KIRISAWA, RYOUHEI; MIKAJIRI, YOSHIMASA; OOTA, SHIGETO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 024796/0979 →
Priority Claims (1)
JP 2009-251891 · Nov 2, 2009 · national
Continuity (1)
Related Publication 20110103153A1 · May 5, 2011