Diode assembly
View Patent ↗A diode assembly comprising first and second diodes each having a different breakdown voltage, each of the first and second diodes comprising a semiconductor substrate; an electrically conducting channel layer on the semiconductor substrate; an upper semiconductor layer on the channel layer, the upper semiconductor layer comprising a recess; first and second ohmic contacts on the upper semiconductor layer on opposite sides of the recess, the ohmic contacts being connected together to form a first diode contact; a gate electrode within the recess, the gate electrode forming a second diode contact; wherein the area of the recess of the first diode covered by the first gate electrode is different to the area of the recess of the second diode covered by the second gate electrode.
1. A method of manufacture of a diode assembly comprising the steps of:
providing a semiconductor substrate, the substrate having an electrically conducting channel layer thereon and an upper semiconductor layer on the channel layer;
providing a first covering layer on the upper semiconductor layer, the covering layer having first and second recess defining apertures thereon;
etching first and second recesses in the semiconductor layer through the first and second recess defining apertures respectively;
providing a second covering layer having first and second gate defining apertures therein;
depositing first and second gates in the first and second recesses through the first and second gate defining apertures respectively to form first and second diodes;
wherein the area of the first recess covered by a first gate electrode is different to the area of the second recess covered by a second gate electrode, such that the first and second diodes have different breakdown voltages.
2. A method as claimed in claim 1 , wherein the second covering layer is provided on the first covering layer with the gate defining apertures extending through recess defining apertures.
3. A method as claimed in claim 1 , wherein the first covering layer is removed before the second covering layer is provided on the upper semiconductor layer.
4. The method of claim 1 , wherein providing the semiconductor substrate comprises providing a GaAs substrate.
5. The method of claim 1 , further comprising forming a Field Effect Transistor (FET) with at least one of the first and second diodes.
6. The method of claim 1 , wherein etching first and second recesses comprises etching recesses having respective flat bases between respective side walls.
7. The method of claim 1 , further comprising forming at least one further diode.
8. The method of claim 6 , wherein depositing the first gate comprises depositing the first gate such that a distance between an edge of the first gate and its respective side walls is d1 and depositing the second gate comprises depositing the second gate such that a distance between an edge of the second gate and its respective side walls is d2, wherein d1 is different than d2.
9. The method of claim 8 , wherein etching first and second recesses comprises etching recesses having different widths.
10. The method of claim 9 , wherein other than the different widths, the first diode and the second diode are substantially the same.