IP Library Granted Patent US 8,351,185
Granted Patent B2
US 8,351,185 · App. 12/853,712 · Granted Jan 8, 2013

Electronic component and manufacturing method thereof

Assignee: TDK Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,351,185
App. No.
12/853,712
Granted
Jan 8, 2013
Kind
B2
Abstract

The invention provides an electronic component and a manufacturing method thereof that can achieve an improved adhesion strength when the electronic component is solder-mounted onto an external substrate and can thereby obtain considerably improved electric properties and reliabilities, etc. An electronic component, which is a capacitor 1 , has: a circuit element 5 a formed on a substrate 2 ; an electrode layer 5 b connected to the circuit element 5 a ; passivation layers 6 and 8 that cover the electrode layer 5 b ; and terminal electrodes 9 a and 9 b connected to the electrode layer 5 b via via-conductors Va and Vb formed through the passivation layers 6 and 8 , the terminal electrodes 9 a and 9 b being formed to cover the side wall of the passivation layers 6 and 8 . Since the pad electrodes 9 a and 9 b are formed so as to cover the passivation layers 6 and 8 across their uppermost surfaces and side walls, the area of contact between the pad electrodes 9 a and 9 b and the solder for solder-mounting increases, and the capacitor 1 can consequently exhibit an improved adhesion strength.

Claims (25)

1. An electronic component comprising:

a lower electrode formed on a top surface of a substrate, the low electrode comprising a side wall and a top surface;

a dielectric layer that covers (1) the side wall, (2) a part of the top surface of the lower electrode, and (3) a part of the top surface of the substrate around the lower electrode;

a circuit element connected to the lower electrode;

an electrode layer formed on the dielectric layer;

a passivation layer that covers the electrode layer; and

a terminal electrode disposed on a top part of the passivation layer and connected to the electrode layer via a via-conductor formed through the passivation layer,

wherein:

the terminal electrode integrally extends from the top part of the passivation layer along a side wall of the passivation layer and also along an edge portion of the top surface of the substrate;

one end of the terminal electrode is located on the side wall of the passivation layer; and

a part of the edge portion is left uncovered.

2. The electronic component according to claim 1 , wherein the passivation layer includes: a first passivation layer formed above the substrate; and a second passivation layer formed on the first passivation layer and inside an area where the first passivation layer is formed.

3. The electronic component according to claim 2 , wherein the second passivation layer has a substrate side surface that faces the substrate and a terminal electrode side surface that faces the terminal electrode, the substrate side surface of the second passivation layer has a smaller area than the terminal electrode side surface of the second passivation layer; and the side wall of the passivation layer has a reverse-tapered surface.

4. The electronic component according to claim 1 , wherein the electronic component is a capacitor.

5. A method for manufacturing an electronic component, comprising the steps of:

forming a lower electrode on a top surface of a substrate, the low electrode comprising a side wall and a top surface;

forming a dielectric layer that covers (1) the side wall, (2) a part of the top surface of the lower electrode, and (3) a part of the top surface of the substrate around the lower electrode;

forming a circuit element connected to the lower electrode;

forming an electrode layer on the dielectric layer;

forming a passivation layer that covers the electrode layer;

forming a via-conductor that extends through the passivation layer; and

disposing a terminal electrode so that the terminal electrode is connected to the electrode layer via the via-conductor and integrally extends from a top part of the passivation layer along a side wall of the passivation layer and also along an edge portion of the top surface of the substrate;

wherein:

one end of the terminal electrode is located on the side wall of the passivation layer; and

a part of the edge portion is left uncovered.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2010
From: OHTSUKA, TAKASHI; CHOI, KYUNG-KU; NAMIKAWA, TATSUO; YAMAGUCHI, HITOSHI
To: TDK CORPORATION
Reel/Frame 024818/0896 →
Priority Claims (1)
JP 2009-192589 · Aug 21, 2009 · national
Continuity (1)
Related Publication 20110044011A1 · Feb 24, 2011