Method and apparatus for jitter reduction
View Patent ↗A low bandwidth phase lock loop (PLL) arranged in a dual-loop configuration is disclosed. The first loop is a standard loop configuration using a crystal oscillator as a reference clock. The loop parameters for this first PLL can be optimized to work over a wide range of output frequencies, and with a minimum amount of jitter. The first loop outputs a reference signal, which is a VCO output. The second loop comprises a bang-bang detector configured to drive a digital loop filter, which then drives a phase interpolator. The phase interpolator manipulates the output phase. Since phase and frequency are related, where frequency is the derivative of phase, small frequency offsets can be made using a phase control signal, generated within the second loop based on the relation between the reference signal and the clock input signal. The second loop sets the jitter transfer bandwidth of the system.
1. A method for reducing jitter in a received clock input signal, the received input signal having a second frequency and a second phase comprising:
receiving a high frequency clock signal based on a reference signal, the reference signal at a first frequency and a first phase, the high frequency clock signal at the first frequency and the first phase;
receiving a clock input signal at a second frequency and at a second phase, wherein the second frequency and the second phase is different than the first frequency and the first phase;
receiving the high frequency clock signal at a phase interpolator;
processing the high frequency clock signal with the phase interpolator based on input from a loop filter to generate a high frequency clock output which has less jitter than the high frequency clock signal;
receiving the clock input signal and a divided version of the high frequency clock output at a phase detector;
processing the clock input signal and the divided version of the high frequency clock output with the phase detector to generate one or more loop filter input signals to a loop filter;
receiving the one or more loop filter input signals at a loop filter; and
processing the one or more loop filter input signals with the a loop filter to generate the input to the phase interpolator, wherein the processing by the phase interpolator, the phase detector, and the loop filter occur in the digital domain.
2. The method of claim 1 , wherein a first phase lock loop generates the high frequency clock signal.
3. The method of claim 1 , wherein processing the high frequency clock signal and the clock input signal comprises changing the phase of the high frequency clock signal to match the phase of the clock input signal.
4. The method of claim 1 , wherein the high frequency clock signal provided to the phase interpolator is generated by an integer phase lock loop fractional-N phase lock loop, delay locked loop, or a high-Q oscillator.
5. The method of claim 1 , further comprising comparing the clock input signal and a version of the phase interpolator output to create lead/lag signal which is processed to calculate the input to the phase interpolator from the loop filter.
6. The method of claim 1 , wherein the input to the phase interpolator from the loop filter comprises a phase control signal.
7. A system for reproducing a clock input signal to reduce jitter from the clock input signal, the clock input signal at a first frequency, the system comprising:
a first loop, the first loop comprising:
a phase detector configured to compare a reference signal to a first divider output to create at least one first lead/lag signal representing the phase relation between the reference signal to the first divider output;
a loop filter configured to processes the at least one lead/lag signal to create a control voltage;
a voltage controlled oscillator configured to generate a VCO output signal responsive to the control voltage;
a divider configured to change the frequency of the VCO output signal to create the first divider output; and
a second loop, the second loop being digital and comprising:
a loop filter configured to process at least one second lead/lag signal to generate a phase control signal;
a phase interpolator configured to receive the phase control signal and adjust the phase of the VCO output signal from the voltage controlled oscillator based on the phase control signal to create a phase interpolator output matching the clock input signal but with less jitter than the clock input signal;
a divider configured to change the frequency of the phase interpolator output to create a second divider output; and
a phase detector configured to compare the clock input signal to the second divider output to create the at least one second lead/lag signal.
8. The system of claim 7 , wherein the first loop further comprises a signal generator configured to generate the reference signal.
9. The method of claim 8 , wherein the signal generator comprise a crystal oscillator.
10. The system of claim 7 , wherein the phase control signal comprises a digital signal representing a phase shift to be applied to the VCO output signal.
11. The system of claim 7 , wherein the VCO output signal has a frequency matching a frequency of the clock input signal and phase interpolator shifts a phase of the VCO output signal match a phase of the clock input signal according to the phase control signal.
12. A system for reproducing a clock input signal to reduce jitter from the clock input signal, the clock input signal at a first frequency, the system comprising:
a first loop, the first loop comprising:
a phase detector configured to compare a reference signal to a first divider output to create at least one first lead/lag signal representing the phase relation between the reference signal to the first divider output;
a loop filter configured to processes the at least one lead/lag signal to create a control voltage;
a voltage controlled oscillator configured to generate a VCO output signal responsive to the control voltage;
a divider configured to change the frequency of the VCO output signal to create the first divider output; and
a second loop, the second loop comprising:
a loop filter configured to process at least one second lead/lag signal to generate a phase control signal which comprises a digital signal representing a phase shift to be applied to the VCO output signal;
a phase interpolator configured to receive the phase control signal and adjust the phase of the VCO output signal from the voltage controlled oscillator based on the phase control signal to create a phase interpolator output matching the clock input signal but with less jitter than the clock input signal;
a divider configured to change the frequency of the phase interpolator output to create a second divider output; and
a phase detector configured to compare the clock input signal to the second divider output to create the at least one second lead/lag signal.
13. The system of claim 12 , wherein the first loop further comprises a signal generator configured to generate the reference signal.
14. The method of claim 13 , wherein the signal generator comprise a crystal oscillator.
15. The system of claim 12 , wherein the VCO output signal has a frequency matching a frequency of the clock input signal and phase interpolator shifts a phase of the VCO output signal match a phase of the clock input signal according to the phase control signal.