THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE HAVING THE SAME, AND METHOD OF FABRICATING THE SAME
A thin film transistor (TFT), a method of fabricating the same, an organic light emitting diode (OLED) display device having the same, and a method of fabricating the same. The TFT includes a substrate; a buffer layer disposed on the substrate; a semiconductor layer disposed on the buffer layer; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer and corresponding to the semiconductor layer; and source and drain electrodes insulated from the gate electrode, and electrically connected to the semiconductor layer. Here, the semiconductor layer includes a plurality of seed regions separated from each other by a distance of 50 μm or more.
1 . A thin film transistor (TFT), comprising:
a substrate;
a buffer layer disposed on the substrate;
a semiconductor layer disposed on the buffer layer;
a gate insulating layer disposed on the semiconductor layer;
a gate electrode disposed on the gate insulating layer and corresponding to the semiconductor layer; and
source and drain electrodes insulated from the gate electrode, and electrically connected to the semiconductor layer,
wherein the semiconductor layer includes a plurality of seed regions separated from each other by a distance of 50 μm or more.
2 . The TFT according to claim 1 , wherein each of the seed regions includes a plurality of metal silicides.
3 . The TFT according to claim 1 , wherein each of the seed regions has a size of about 2 to 10 μm.
4 . The TFT according to claim 1 , wherein the semiconductor layer includes one selected from the group consisting of Ni, Pd, Ag, Au, Al, Sn, Sb, Cu, Tr and Cd.
5 . A method of fabricating a TFT, comprising:
providing a substrate;
forming a buffer layer on the substrate;
forming an amorphous silicon layer on the buffer layer;
forming a capping layer on the amorphous silicon layer, the capping layer having one or more holes exposing the amorphous silicon layer;
treating the substrate with plasma;
providing a metal catalyst solution to the holes;
annealing the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer;
removing the capping layer;
forming a semiconductor layer by crystallizing the polycrystalline silicon layer;
forming a gate insulating layer on the substrate;
forming a gate electrode on the gate insulating layer; and
forming source and drain electrodes insulated from the gate electrode and connected to the semiconductor layer.
6 . The method according to claim 5 , wherein the plasma treatment is performed using nitrogen-based or ammonia-based plasma.
7 . The method according to claim 5 , further comprising sintering and annealing the substrate after forming the metal catalyst solution.
8 . The method according to claim 7 , wherein the sintering is performed at about 30 to 45° C.
9 . The method according to claim 7 , wherein the annealing is performed at about 90 to 110° C.
10 . The method according to claim 5 , wherein the metal catalyst solution includes one selected from the group consisting of Ni, Pd, Ag, Au, Al, Sn, Sb, Cu, Tr and Cd.
11 . An organic light emitting diode (OLED) display device, comprising:
a substrate;
a buffer layer disposed on the substrate;
a semiconductor layer disposed on the buffer layer;
a gate insulating layer disposed on the semiconductor layer;
a gate electrode disposed on the gate insulating layer and corresponding to the semiconductor layer;
source and drain electrodes insulated from the gate electrode and electrically connected to the semiconductor layer;
an insulating layer disposed on the substrate; and
a first electrode electrically connected to one of the source and drain electrodes, an organic layer and a second electrode,
wherein the semiconductor layer includes a plurality of seed regions, separated from each other by a distance of 50 μm or more.
12 . The device according to claim 11 , wherein each of the seed regions includes a plurality of metal silicides.
13 . The device according to claim 11 , wherein each of the seed regions has a size of about 2 to 10 μm.
14 . The device according to claim 11 , wherein the semiconductor layer includes one selected from the group consisting of Ni, Pd, Ag, Au, Al, Sn, Sb, Cu, Tr and Cd.
15 . A method of fabricating an Organic Light Emitting Diode (OLED) display device, comprising:
providing a substrate;
forming a buffer layer on the substrate;
forming an amorphous silicon layer on the buffer layer;
forming a capping layer on the amorphous silicon layer, the capping layer having one or more holes exposing the amorphous silicon layer;
treating the substrate with plasma;
providing a metal catalyst solution to the holes;
annealing the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer;
removing the capping layer;
forming a semiconductor layer by crystallizing the polycrystalline silicon layer;
forming a gate insulating layer on the substrate;
forming a gate electrode on the gate insulating layer;
forming source and drain electrodes insulated from the gate electrode and connected to the semiconductor layer;
forming an insulating layer on an entire surface of the substrate; and
forming a first electrode electrically connected to one of the source and drain electrodes, an organic layer and a second electrode.
16 . The method according to claim 15 , wherein the plasma treatment is performed using nitrogen-based or ammonia-based plasma.
17 . The method according to claim 15 , further comprising, sintering and annealing the substrate after forming the metal catalyst solution.
18 . The method according to claim 17 , wherein the sintering is performed at about 30 to 45° C.
19 . The method according to claim 17 , wherein the annealing is performed at about 90 to 110° C.
20 . The method according to claim 15 , wherein the metal catalyst solution includes one selected from the group consisting of Ni, Pd, Ag, Au, Al, Sn, Sb, Cu, Tr and Cd.
21 . The method according to claim 5 , wherein a diameter of each one of the holes, through which the amorphous silicon layer is exposed, is in a range between about 2 to 10 μm.
22 . The method according to claim 15 , wherein a diameter of each one of the holes, through which the amorphous silicon layer is exposed, is in a range between about 2 to 10 μm.
23 . The method according to claim 5 , wherein the metal catalyst solution controls an amount of remaining metal catalysts on the one or more holes.
24 . The method according to claim 23 , wherein an areal density of the remaining metal catalysts is in a range between 10 11 to 10 15 atoms/cm 2 .
25 . The method according to claim 15 , wherein the metal catalyst solution controls an amount of remaining metal catalysts on the one or more holes.
26 . The method according to claim 25 , wherein an areal density of the remaining metal catalysts is in a range between 10 11 to 10 15 atoms/cm 2 .