System and method for digital control of amplifier gain with reduced zipper noise
View Patent ↗A digitally-controlled analog gain circuit supports at plurality of gain settings in which gain changes are made from a first setting to a new setting in response to a clocking signal of a non-uniform rate. The non-uniform rate clocking signal can be created pseudo randomly by applying a periodic sequence of clock pulses to a linear feedback shift register. Alternatively, the non-uniform rate clock signal can be created by applying a noise source to a phase detector input of a phase locked loop. The clocking signal can be generated by an oscillator, or as a sequence of pulses output by a zero crossing detector. Finally, the gain circuit can apply positive gain to the signal. Alternatively, the gain circuit can apply a negative gain (attenuation) to the signal.
1. A digitally controlled gain control system for digitally controlling the gain of an amplifier, comprising:
an amplifier configured to amplify an analog input signal in accordance with a gain represented by a digital gain control signal applied to the system; and
a clock configured to generate a clocking signal so that the gain can be set in increments of gain change in response to a change in the gain represented by a respective change in the digital gain control signal;
wherein the increments of gain change are provided in non-uniform time increments, wherein the clock includes a clock generator configured to generate a periodic clock signal and a clock randomizer configured to generate a pseudo-randomized clock signal in response to the periodic clock signal.
2. A system according to claim 1 , wherein the amplifier supports a plurality of discrete gain settings.
3. A system according to claim 1 , wherein the clock includes a clock signal randomizer configured so that clocking signal is generated in non-uniform time increments that vary pseudo-randomly.
4. A system according to claim 1 , wherein the clock randomizer includes a linear feedback shift register (LFSR).
5. A system according to claim 1 , wherein the clock randomizer includes a phase lock loop.
6. A system according to claim 5 , wherein the phase lock loop includes a signal summer for adding noise into the phase lock loop.
7. A system according to claim 6 , wherein the phase lock loop includes a voltage controlled oscillator.
8. A system according to claim 1 , wherein the clock randomizer includes a zero crossing detector configured to provide a signal to the clock randomizer in response to detection of the analog signal being zero.
9. A system according to claim 1 , wherein the system applies positive gain to the analog signal.
10. A system according to claim 1 , wherein the system applies negative gain to the analog signal.
11. A method of digitally controlling the gain of an amplifier, comprising:
amplifying an analog input signal in accordance with a gain represented by a digital gain control signal; and
generating a clocking signal so that the gain can be set in increments of gain change in response to a change in the gain represented by a respective change in the digital gain control signal;
wherein the increments of gain change are provided in non-uniform time increments; and
wherein generating a clocking signal comprises generating a periodic clock signal and generating a pseudo-randomized clock signal in response to the periodic clock signal.
12. A method according to claim 11 , wherein the amplifier supports a plurality of discrete gain settings each presented by a different digital gain control signal.
13. A method according to claim 11 , wherein generating the clocking signal includes generating the clocking signal in non-uniform time increments that vary pseudo-randomly.
14. A method according to claim 11 , wherein generating a pseudo-randomized clock signal includes processing the periodic clock signal with a linear feedback shift register (LFSR).
15. A method according to claim 11 , wherein generating a randomized clock signal includes processing the periodic clock signal with a phase lock loop.
16. A method according to claim 15 , wherein processing the periodic clock signal with a phase lock loop includes processing the periodic clock signal with a signal summer for adding noise into a signal path of the phase lock loop.
17. A method according to claim 15 , wherein processing the periodic clock signal with a phase lock loop includes processing the periodic clock signal with a voltage controlled oscillator.
18. A method according to claim 11 , wherein generating a clocking signal so that the gain can be set in increments of gain change in response to a change in the gain represented by a respective change in the digital gain control signal includes generating the clocking signal in response to detection of the analog signal crossing zero.
19. A method according to claim 11 , wherein the method applies positive gain to the analog signal.
20. A method according to claim 11 , wherein the method applies negative gain to the analog signal.