IP Library Granted Patent US 8,368,230
Granted Patent B2
US 8,368,230 · App. 12/857,893 · Granted Feb 5, 2013

Electronic part and method of manufacturing the same

Inventor: Masateru Koide (Kawasaki, JP)
Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 8,368,230
App. No.
12/857,893
Granted
Feb 5, 2013
Kind
B2
Abstract

A multi-chip module includes a package board, a plurality of chips, and a wiring board. The plurality of chips are horizontally disposed on the package board. The plurality of chips are electrically connected with the package board, and respectively provided with via holes which penetrate through the plurality of chips. The plurality of chips are respectively provided with circuits at surfaces facing the package board. The wiring board is disposed on an opposite side to the package board across the plurality of chips. The wiring board includes a wiring pattern which is electrically connecting adjacent chips one another. The circuit is electrically connected to the wiring pattern through the via holes.

Claims (15)

1. An electronic part comprising:

a package board;

a plurality of chips horizontally disposed on the package board, electrically connected with the package board, respectively provided with via holes penetrating through the plurality of chips, and respectively provided with circuits at surfaces facing the package board; and

a wiring board disposed on an opposite side to the package board across the plurality of chips, and including a wiring pattern electrically connecting adjacent chips one another,

wherein the circuit is electrically connected to the wiring pattern through the via holes.

2. The electronic part of claim 1 , wherein the wiring pattern is formed by a semiconductor manufacture equipment.

3. The electronic part of claim 1 , wherein at least one of the plurality of chips has a different thickness as compared to another chip of the plurality of chips.

4. The electronic part of claim 1 , wherein the wiring board includes:

a silicon substrate; and

an insulating layer disposed on the silicon substrate, and the wiring Pattern is formed in the insulating layer.

5. A method of manufacturing an electronic part comprising:

disposing a plurality of chips horizontally on a package board, each of the plurality of chips including a circuit facing the package board;

polishing opposite surfaces of the plurality of chips with respect to the circuit to level the opposite surfaces of the plurality of chips;

mounting a wiring board on polished surfaces of the plurality of chips; and

electrically connecting the chips to one another with a wiring pattern provided in the wiring board.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2010
From: KOIDE, MASATERU
To: FUJITSU LIMITED
Reel/Frame 024849/0967 →
Priority Claims (1)
JP 2009-191280 · Aug 20, 2009 · national
Continuity (1)
Related Publication 20110042824A1 · Feb 24, 2011