System comprising a semiconductor device and structure

1. A mobile device comprising a semiconductor device, the semiconductor device comprising:

a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying said first single crystal silicon layer, wherein said first alignment marks are detectable by a lithography tool to locate the lithography tool with respect to the first single crystal silicon layer; and

a second single crystal silicon layer overlying said at least one metal layer;

wherein said second single crystal silicon layer comprises a plurality of second transistors and second alignment marks, wherein said second alignment marks are detectable by the lithography tool to locate the lithography tool with respect to the second single crystal silicon layer,

wherein said second transistors are defined and aligned to said first transistors based on said first alignment marks and said second alignment marks.

2. A mobile device according to claim 1 , wherein said second single crystal silicon layer is less than 0.4 micron thick.

3. A mobile device according to claim 1 , wherein said second transistors are planar transistors.

4. A mobile device according to claim 1 , wherein said second transistors comprise junction-less transistors.

5. A mobile device according to claim 1 , wherein said second transistors comprise Recessed Channel Array Transistors (RCAT).

6. A mobile device according to claim 1 , wherein said second single crystal silicon layer further comprises through vias through said second single crystal silicon layer,

wherein said through vias are aligned in a first direction to said first alignment marks and aligned in a second direction to said second alignment marks.

7. A mobile device according to claim 1 , wherein said second transistors are gate-last transistors.

8. A system comprising a semiconductor device, the semiconductor device comprising:

a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials, wherein said first alignment marks are detectable by a lithography tool to locate the lithography tool with respect to the first single crystal silicon layer; and

a second single crystal silicon layer overlying said at least one metal layer;

wherein said second single crystal silicon layer comprises a plurality of second transistors comprising P type transistors and N type transistors;

wherein at least one of said second transistors is defined and aligned to said first alignment marks.

9. A system according to claim 8 , wherein said second single crystal silicon layer is less than 0.4 micron thick.

10. A system according to claim 8 , wherein said second transistors are planar transistors.

11. A system according to claim 8 , wherein said second transistors comprise Recessed Channel Array Transistors (RCATs).

12. A system according to claim 8 , wherein said second transistors comprise junction-less transistors.

13. A system according to claim 8 ,

wherein said second single crystal silicon layer comprises second alignment marks and through vias through said second single crystal silicon layer, wherein said second alignment marks are detectable by a lithography tool to locate the lithography tool with respect to the second single crystal silicon layer, and

wherein said through vias are aligned in a first direction to said first alignment marks and in a second direction to said second alignment marks.

14. A system according to claim 8 , wherein said second transistors are gate-last transistors.