Data aware scheduling on heterogeneous platforms

1. A system for data-aware scheduling of applications on a discrete heterogeneous platform having at least one central processing unit (CPU) and at least one accelerator having at least one graphics processing unit (GPU), comprising:

a function call handling module configured to intercept, analyze, and schedule library calls on a processing element, comprising:

a function call interception module configured to intercept function calls to predefined library kernels having one or more CPU library implementation and one or more accelerators library implementation;

a function call analysis module configured to analyze argument size and location of requested data used by a predefined library kernel; and

a function call redirection module configured to schedule library calls and data transfers; and

a memory unification module, configured to keep data coherent between different memories associated with the at least one CPU and the at least one accelerator based on the output of the function call redirection module by synchronizing CPU memory and accelerator memory; and

in response to the analyzed argument size and the location of requested data, the function call analysis module configured to determine whether the CPU or one of the accelerators would most efficiently execute the predefined library kernel, and if the data is not located at a fastest processor for executing the predefined library kernel;

the function call analysis module configured to compare a time needed to transfer data having the analyzed argument size to a threshold;

if the time needed to transfer data having the analyzed argument size is greater than the threshold, scheduling the predefined library kernel at a first processing element currently storing the requested data;

if the time needed to transfer data is below the threshold, transferring the requested data to a more efficient processing element and assigning the predefined library kernel at the more efficient processing element at a second location.

2. The system of claim 1 , wherein the function call analysis module is configured to analyze a size of the parameters and a location of the corresponding data and is further configured to use profiling information to estimate the execution time of the function call on the at least one CPU and the at least one accelerator.

3. The system of claim 1 , wherein the function call redirection module is configured to redirect function calls to the most suitable library implementation based on the output of the function call analysis module.

4. The system of claim 1 , wherein the memory unification module is configured to synchronize CPU and accelerator memory and to maintain coherence by triggering data transfers between CPU memory and accelerator memory.

5. The system of claim 4 , wherein the memory unification module is configured to operate transparently, such that programs using the system interact with a single virtual shared memory system for the at least one CPU and the at least one accelerator.

6. The system of claim 1 , wherein the memory unification module maintains a mapping between the content of CPU and accelerator memories and provides an interface to the function call handling module.

7. The system of claim 6 , wherein the memory unification module provides an interface that is configured to trigger CPU-to-accelerator and accelerator-CPU data transfers.

8. The system of claim 1 , wherein the memory unification module is configured to maintain a synchronization status for all CPU data blocks that have been mapped to an accelerator.

9. The system of claim 8 , wherein the memory unification module is configured to update the synchronization status of the data blocks in response to data access operations.

10. The system of claim 8 , wherein the memory unification module is configured to maintain a list of memory locations that are mapped to the accelerators and integrate with an operating system by via a page fault handler of the operating system, such that page faults are invoked when the CPU accesses memory locations that are mapped to an accelerator and page faults are serviced by the transfer of data between the CPU and said accelerator.

11. A method for data-aware scheduling of applications on a discrete heterogeneous platform having at least one central processing unit (CPU) and at least one accelerator having at least one graphics processing unit (GPU), comprising:

intercepting, determining, and scheduling library calls on a processing element, comprising;

intercepting function calls to predefined library kernels having one or more CPU library implementation and one or more accelerators library implementation;

determining argument size and location of requested data used by a predefined library kernel; and

scheduling library calls and data transfers; and

keeping data coherent between different memories associated with the at least one CPU and the at least one accelerator based on the output of scheduling library calls and data transfers by synchronizing CPU memory and accelerator memory; and

in response to the determined argument size and the location of requested data, determining whether the CPU or one of the accelerators would most efficiently execute the predefined library kernel, and if the data is not located at a fastest processor for executing the predefined library kernel;

comparing a time needed to transfer data having the determined argument size to a threshold;

if the time needed to transfer data having the determined argument size is greater than the threshold, scheduling the predefined library kernel at a first processing element currently storing the requested data;

if the time needed to transfer data is below the threshold, transferring the requested data to a more efficient processing element and assigning the predefined library kernel at the more efficient processing element at second location.

12. The method of claim 11 , wherein the comparison of the data transfer time to the threshold is further based on an estimated time of execution of the function call on the first and the second processing element.