NAND flash-based storage device with built-in test-ahead for failure anticipation
View Patent ↗A test-ahead feature for non-volatile memory-based mass storage devices to anticipate device failure. The test-ahead feature includes a method performed with a solid-state mass storage device having a controller, a cache memory, and at least one non-volatile memory device. At least a first block is reserved on the at least one non-volatile memory device as a wear-indicator block and a plurality of second blocks are used for data storage. Information is stored corresponding to the number of write and erase cycles encountered by the second blocks during usage of the mass storage device, and the information is accessed to perform wear leveling among the second blocks. The wear-indicator blocks are subjected to an offset number of write and erase cycles in excess of the number of write and erase cycles encountered by the second blocks, after which an integrity check of the first block is performed.
1. A method for predicting a failure of a solid-state mass storage device having a controller, a cache memory, and at least one non-volatile memory device, the method comprising:
reserving at least a first block on the at least one non-volatile memory device as a wear-indicator block and using a plurality of second blocks on the at least one non-volatile memory device for data storage;
storing information corresponding to the number of write and erase cycles encountered by the second blocks during usage of the solid-state mass storage device and accessing the information to perform wear leveling among the second blocks;
subjecting the wear-indicator blocks to an offset number of write and erase cycles that is in excess of the number of write and erase cycles encountered by the second blocks during usage of the solid-state mass storage device; and then
performing integrity checks of the first block.
2. The method of claim 1 , wherein the offset number of write and erase cycles is based on the information used to perform the wear leveling among the second blocks.
3. The method of claim 1 , wherein the information comprises a mean access value of the second blocks based on the number of write and erase cycles encountered by the second blocks during usage of the solid-state mass storage device, and the offset number of write and erase cycles is an increase over the mean access value.
4. The method of claim 1 , wherein the offset number of write and erase cycles is a fixed offset of additional write, read and/or erase cycles to which the wear-indicator block is subjected in excess of the write, read and/or erase cycles to the second blocks.
5. The method of claim 1 , wherein the offset number of write and erase cycles is a percentage-wise offset by which the write, read and/or erase cycles to the wear-indicator block are increased on a percentage basis over the write, read and/or erase cycles to the second blocks.
6. The method of claim 1 , wherein the offset number of write and erase cycles to the first block uses random data samples from a write to the second blocks, averaged samples of writes to the second blocks, or a predefined test pattern to write to the wear-indicator block.
7. The method of claim 1 , wherein the step of performing integrity checks of the first block uses an ECC algorithm to generate a checksum of a data range in the first block and then monitor changes in the bit error rate on subsequent reads of the same data range.
8. The method of claim 1 , further comprising the step of the controller 20 taking corrective action following the performing step, the corrective action being at least one chosen from the group consisting of performing media scrubbing of the second blocks, initiating an error warning, and initiating a back-up of data stored in the second blocks.
9. The method of claim 1 , wherein the at least one non-volatile memory device of the solid-state mass storage device comprises a plurality of non-volatile memory devices.
10. The method of claim 9 , wherein each of the non-volatile memory devices contains a wear-indicator block.
11. The method of claim 9 , wherein only one of the non-volatile memory devices contains a wear-indicator block.
12. A solid-state mass storage device having a controller, a cache memory, and at least one non-volatile memory device, the at least one non-volatile memory device being partitioned into at least a first block as a wear-indicator block and a plurality of second blocks for data storage, the solid-state mass storage device being adapted to subject the wear-indicator block to an offset number of write and erase cycles that is in excess of the number of write and erase cycles encountered by the second blocks during usage of the solid-state mass storage device, the solid-state mass storage device further comprising means for predicting a failure of the second blocks based on a failure of the wear-indicator block.
13. The solid-state mass storage device of claim 12 , further comprising means for storing information corresponding to the number of write and erase cycles encountered by the second blocks during usage of the solid-state mass storage device and accessing the information to perform wear leveling among the second blocks.
14. The solid-state mass storage device of claim 12 , wherein the offset number of write and erase cycles is a fixed offset of additional write, read and/or erase cycles to which the wear-indicator block is subjected in excess of the write, read and/or erase cycles to the second blocks.
15. The solid-state mass storage device of claim 12 , wherein the offset number of write and erase cycles is a percentage-wise offset by which the write, read and/or erase cycles to the wear-indicator block are increased on a percentage basis over the write, read and/or erase cycles to the second blocks.
16. The solid-state mass storage device of claim 12 , wherein the predicting means comprises means for detecting an increase in the bit error rate between consecutive reads of the same data range in the wear-indicator block based on a comparison of the ECC checksum and the corresponding data range.
17. The solid-state mass storage device of claim 12 , wherein the controller is adapted to take a corrective action in response to a failure of the wear-indicator block, the corrective action being at least one chosen from the group consisting of performing media scrubbing of the second blocks, initiating an error warning, and initiating a back-up of data stored in the second blocks.
18. The solid-state mass storage device of claim 12 , wherein the at least one non-volatile memory device of the solid-state mass storage device comprises a plurality of non-volatile memory devices.
19. The solid-state mass storage device of claim 18 , wherein each of the non-volatile memory devices contains a wear-indicator block.
20. The solid-state mass storage device of claim 18 , wherein only one of the non-volatile memory devices contains a wear-indicator block.
21. The method of claim 1 , wherein the at least one non-volatile memory device is a flash memory-based mass storage device.
22. The method of claim 1 , wherein the at least one non-volatile memory device is a NAND flash memory-based mass storage device.
23. The solid-state mass storage device of claim 12 , wherein the at least one non-volatile memory device is a flash memory-based mass storage device.
24. The solid-state mass storage device of claim 12 , wherein the at least one non-volatile memory device is a NAND flash memory-based mass storage device.